Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

Staszewski, Robert Bogdan; Leipold, Dirk; Muhammad, K.; Balsara, Poras T.

doi:10.1109/tcsii.2003.819128

Cited by 166 publications

(71 citation statements)

References 13 publications

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“…Since the varactors, i.e., the DCO input, are digitally controlled, and since the output clock at multi-GHz frequencies is still almost of an acceptable digital waveform shape (the rise and fall times could be as fast as 30 ps), the loop around the DCO, which adjusts its phase and frequency, could now be fully digital, as first proposed in Ref. [36].…”

Section: Digitally Controlled Oscillator (Dco)mentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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This paper presents an all-digital phase-locked loop (ADPLL) architecture in a new light that allows it to significantly save power through complexity reduction of its phase locking and detection mechanisms. The predictive nature of the ADPLL to estimate next edge occurrence of the reference clock is exploited here to reduce the timing range and thus complexity of the fractional part of the phase detection mechanism as implemented by a time-to-digital converter (TDC) and to ease the clock retiming circuit. In addition, the integer part, which counts the DCO clock edges, can be disabled to save power once the loop has achieved lock. It can be widely used in fields of fractional-N frequency multiplication and frequency/phase modulation. The presented principles and techniques have been validated through extensive behavioral simulations as well as fabricated IC chips.

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Section: Digitally Controlled Oscillator (Dco)mentioning

confidence: 99%

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Zhuang

Staszewski

2014

IPSJ Transactions on System LSI Design Methodology

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“…The utilization of digital ∆Σ is not limited to digital-to-analog conversion only. It is also used in analog-to-digital conversion [35][36][37][38], in phase-locked loops [39][40][41][42][43][44][45][46][47][48][49], and as a source to generate dithering signals [50][51][52][53][54][55][56], to segment the DAC further [57,58] and in multiple-input, multiple-output transceivers [59], etc. All of the above signal processing blocks are used for narrow-, wideand ultra-wide-band applications like digital audio [60][61][62], handsets [63][64][65], biomedical [66,67], TV [68][69][70], digital radio tuners [71,72] and wireless infrastructures [73][74][75].…”

Section: Introductionmentioning

confidence: 99%

Complexity and Power Reduction in Digital Delta-Sigma Modulators

Afzal

2015

Linköping Studies in Science and Technology. Dissertations

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Papers A and C are reprinted with permission from IEEE.Cover figure is an illustration of the digital cascaded error-feedback modulator.Printed by LiU-Tryck, Linköping, Sweden 2014 To my parents and teachers AbstractA number of state-of-the-art low power consuming digital delta-sigma modulator (∆Σ) architectures for digital-to-analog converters (DAC) are presented in this thesis. In an oversampling ∆Σ DAC, the primary job of the modulator is to reduce the word length of the digital control signal to the DAC and spectrally shape the resulting quantization noise. Among the ∆Σ topologies, error-feedback modulators (EFM) are well suited for so called digital to digital modulation In order to meet the demands, various modifications to the conventional EFM architectures have been proposed. It is observed that if the internal and external digital signals of the EFM are not properly scaled then not only the design itself but also the signal processing blocks placed after it, may be over designed. In order to avoid the possible wastage of resources, a number of scaling criteria are derived. In this regard, the total number of signal levels of the EFM output is expressed in terms of the input scale, the order of modulation and the type of the loop filter.Further on, it is described that the architectural properties of a unit elementbased DAC allow us to move some of the digital processing of the EFM to the analog domain with no additional hardware cost. In order to exploit the architectural properties, digital circuitry of an arbitrary-ordered EFM is split into two parts: one producing the modulated output and another producing the filtered quantization noise. The part producing the modulated output is removed after representing the EFM output with a set of encoded signals. For both the conventional and the proposed EFM architectures, the DAC structure remains unchanged. Thus, savings are obtained since the bits to be converted are not accumulated in the digital domain but instead fed directly to the DAC.A strategy to reduce the hardware of conventional EFMs has been devised recently that uses multiple cascaded EFM units. We applied the similar approach but used several cascaded modified EFM units. The compatibility issues among the units (since the output of each proposed EFM is represented by the set of encoded signals) are resolved by a number of architectural modifications. The digital processing is distributed among each unit by splitting the primary input bus. It is shown that instead of cascading the EFM units, it is enough to cascade their loop filters only. This leads not only to area reduction but also to the reduction of power consumption and critical path.All of the designs are subjected to rigorous analysis and are described mathev vi Abstract matically. The estimates of area and power consumption are obtained after synthesizing the designs in a 65 nm standard cell library provided by the foundry. Populärvetenskaplig sammanfattning vii viiiPopulärvetenskaplig sammanfattning I denna avhandling presenteras e...

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“…To overcome the limitation of the varactor capacitance, a sigma-delta modulator is used to implement the fine capacitance [3]. In this case, the dithering bits of the sigma-delta modulator need to be increased in order to implement a finer resolution.…”

Section: Introductionmentioning

confidence: 99%

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

Park¹,

Kim²,

Lee³

2013

JSTS:Journal of Semiconductor Technology and Science

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Abstract-This paper presents a wide band, fineresolution digitally controlled oscillator (DCO) with an on-chip 3-D solenoid inductor using the 0.13 µm digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. To control the frequency of the DCO, active capacitor and active inductor are tuned digitally. To cover the wide tuning range, a three-step coarse tuning scheme is used. In addition, the DCO gain needs to be calibrated digitally to compensate for gain variations. The DCO with solenoid inductor is fabricated in 0.13 µm process and the die area of the solenoid inductor is 0.013 mm 2 . The DCO tuning range is about 54 % at 4.1 GHz, and the power consumption is 6.6 mW from a 1.2 V supply voltage. An effective frequency resolution is 0.14 kHz. The measured phase noise of the DCO output at 5.195 GHz is -110.61 dBc/Hz at 1 MHz offset.

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Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS process

Cited by 166 publications

References 13 publications

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

All-Digital RF Phase-Locked Loops Exploiting Phase Prediction

Complexity and Power Reduction in Digital Delta-Sigma Modulators

A Small-Area Solenoid Inductor Based Digitally Controlled Oscillator

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