Digital-to-Time Synthesizers: Separating Delay Line Error Spurs and Quantization Error Spurs

Talwalkar, Sumit A.

doi:10.1109/tcsi.2013.2249152

Cited by 11 publications

(3 citation statements)

References 19 publications

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“…Any additional spurs which are introduced by a DTC need to be characterized. Investigations for a DTC based on delay elements have been published in [11], [12]. The results show that the resolution and linearity are major requirements for a DTC with respect to spurs.…”

mentioning

confidence: 99%

Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers

Preissl

Preyler

Springer

et al. 2021

IEEE Trans. Circuits Syst. I

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Digital-to-time converters (DTCs) are a promising technology for radio frequency (RF) transceivers but are prone to spur generation. A common approach to change the spurious emissions to a spur-free shape is a method called dithering. The power added due to dithering is an important aspect of this approach and gives raise to investigations on additive dither as well as methods for subtractive dithering. This work presents a mathematical model for dithering DTC-based local oscillator (LO) generators. It proposes concepts for the application of subtractive dither and it introduces a novel generalization of quantization-dither to allow for optimal dithering of nonlinear quantizers.

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mentioning

confidence: 99%

Dithering Concepts for Spur-Free Nonlinear DTC-Based Frequency Synthesizers

Preissl

Preyler

Springer

et al. 2021

IEEE Trans. Circuits Syst. I

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show abstract

“…Considering the retiming techniques mentioned in section 1.1, those controlled digitally can be regarded as implementations of DTCs. A broad definition of a DTC would include also tapped delay lines and Delay-Locked Loops (DLLs) [44][45][46]. However in this thesis, we will strictly limit the term DTC to a "single shot" device that produces one output edge in response to an input edge.…”

Section: State-of-the-art Dtcsmentioning

confidence: 99%

“…DTCs for spur correction have been proposed inside DPC systems [28,44,45,93], while in this chapter we introduce a DTC in a DFC architecture, targeting 50 % duty-cycle pulse-output. We will analyze the DTC specifications (resolution, linearity) that impact the output-spectrum purity and derive simple equations to predict the maximum spurs, to facilitate the system design.…”

Section: Chapter 4 Pulse-output Dfcs: Reducing Spurs With a Dtcmentioning

confidence: 99%