Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

Jiang, Wenjie; Le, Huy; Kim, S.A.; Chung, J.E.; Wu, Yu-Jen; Bendix, P.; Jensen, J.F.; Ardans, R.; Prasad, Sharat C.; Kapoor, Ashish; Kopley, T.E.; Dungan, T.E.; Marcoux, P.

doi:10.1109/icmts.1997.589335

Cited by 3 publications

(1 citation statement)

References 14 publications

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“…all transistors switch at the clock frequency), and therefore based digital circuit degradation studies on the degradation of ring oscillators. Typically, ring oscillators are built in such a way that a stage in the loop is designed to have the terminals of that particular stage's individual transistors connected to pads [23]. This allows one to monitor the degradation of circuit frequency fro as well as individual N-and P-MOS AId.…”

Section: Ac Correction Factormentioning

confidence: 99%

On the methodology of assessing hot-carrier reliability of analog circuits

Marcoux²,

Jiang³

et al.

2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)

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As VLSI technologies are scaled into the deep submicron region, traditional hot-carrier reliability criteria can no longer be satisfied. A more realistic reliability criteria based on circuit performance, that takes into account both the physics of the degradation as well as its impact on device and circuit performance, is necessary. The current method of assessing hot-carrier reliability through simulation is an ad hoc approach, requires extensive tool calibration and yields no insights to the problem at hand. This study proposes a unified approach to evaluating hot-carrier reliability of analog circuits.First, by choosing the appropriate device model that can link device behavior to circuit performance, hot-carrier degradation can be treated as perturbations to device parameters, and therefore, can be correctly reflected at the circuit level. Second, device-level performance parameters (such as I d , gm, and gds) are studied in detail as functions of process parameters VT and J-l. This allows easy prediction of device-level parameter degradation by monitoring just two process parameters. Third, by taking advantage of well-developed circuit-analysis techniques, the small-signal device parameters gm and gds are used as independent variables to Circuit Degradation Models (CDMs), where the degradation of circuitlevel DC parameters of analog sub circuits can be modeled reasonably well as 'perturbations' in VT and J-l. This provides insights into how circuits may behave as various devices within the circuit degrade due to hot-carrier degradation. Finally, by analyzing the analog design space and examining hot-carrier degradation factors that are important to analog circuits, reliability and performance curves are presented as a way for designers and reliability engineers to define a more realistic and circuit-based criteria for hot-carrier degradation.

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Section: Ac Correction Factormentioning

confidence: 99%

On the methodology of assessing hot-carrier reliability of analog circuits

Marcoux²,

Jiang³

et al.

2000 IEEE International Integrated Reliability Workshop Final Report (Cat. No.00TH8515)

Self Cite

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A combined test structure with ring oscillator and inverter chain for evaluating optimum high-speed/low-power operation

Matsuda

Iwata

Ohzone³

et al.

International Conference on Microelectronic Test Structures, 2003.

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A test structure combined with a ring oscillator, an inverter chain and an embedded monitor inverter, which allows accurate internal node access, is proposed. Vdd and well-hias dependence of gate delay and supply current measured hy both ring oscillator and inverter chain scheme. V, control method by well biasing, particularly to forward direction, is effective for high speed operation under low supply voltage. The new test structure can he utilized to evaluate optimum conditions for high-speed/low-power operations as well as high-reliability operations.

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