2013 25th International Conference on Microelectronics (ICM) 2013
DOI: 10.1109/icm.2013.6735023
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Digital synthesis architecture for modulation and demodulation

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Cited by 2 publications
(5 citation statements)
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“…Although the complexity reduction is not more important and the maximum frequency is lower than the dedicated hardware architecture (Velcro), the great advantage of the proposed architecture is the higher flexibility and its use in a regular architecture. This offered flexibility increases the parallelism of the processing by sharing common resources between the algorithms, which leads to improve the calculation speed [7][8][9][10]. The FPGA implementation results of the proposed architecture and previous works that share some common functionality of the proposed architecture are given in Table 3 for different word-lengths (n).…”
Section: Fpga Implementation Results and Performance Comparisonsmentioning
confidence: 99%
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“…Although the complexity reduction is not more important and the maximum frequency is lower than the dedicated hardware architecture (Velcro), the great advantage of the proposed architecture is the higher flexibility and its use in a regular architecture. This offered flexibility increases the parallelism of the processing by sharing common resources between the algorithms, which leads to improve the calculation speed [7][8][9][10]. The FPGA implementation results of the proposed architecture and previous works that share some common functionality of the proposed architecture are given in Table 3 for different word-lengths (n).…”
Section: Fpga Implementation Results and Performance Comparisonsmentioning
confidence: 99%
“…It is just juxtaposition of several standard chains and the ''re-configuration'' is simply performed by a switch from one to another. Moreover, its scalability is limited by the standards considered and the complexity of its implementation remains maximum [7][8][9]. For instance, [7] proposes to compare its reconfigurable architecture with the Velcro technique using the Gain in terms of ALUTs, the critical path delay in nanoseconds, the memory saving and performance-to-cost ratio ''g'' defined by 1/(TC)*10 6 , where C is the number of logic blocks related to the cost of a FPGA-based circuit while T the execution time in nanoseconds (ns).…”
Section: Introductionmentioning
confidence: 99%
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“…These different architectures proposed for these operations and functions have many similarities points between them [2][3]. These similarities are exploited to propose a new architecture entirely digital, and "universal", able to take charge of functionalities previously managed by different circuits [4]. Many previous works propose various implementations of generic architectures.…”
Section: Introductionmentioning
confidence: 99%