Digital Signal Processing with Field Programmable Gate Arrays

Meyer-Baese, Uwe

doi:10.1007/978-3-642-45309-0

Cited by 78 publications

(34 citation statements)

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“…A DSP is a specialized microprocessor that has an architecture optimized for the fast operational needs of digital signal processing. A DSP process data in real time, making it ideal for applications that cannot tolerate delays [35], [36].…”

Section: Fpga Implementation Of the Bp Algorithmmentioning

confidence: 99%

Efficient Implementation of the Backpropagation Algorithm in FPGAs and Microcontrollers

Ortega-Zamorano

Jerez

Munoz

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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The well-known backpropagation learning algorithm is implemented in a field-programmable gate array (FPGA) board and a microcontroller, focusing in obtaining efficient implementations in terms of a resource usage and computational speed. The algorithm was implemented in both cases using a training/validation/testing scheme in order to avoid overfitting problems. For the case of the FPGA implementation, a new neuron representation that reduces drastically the resource usage was introduced by combining the input and first hidden layer units in a single module. Further, a time-division multiplexing scheme was implemented for carrying out product computations taking advantage of the built-in digital signal processor cores. In both implementations, the floating-point data type representation normally used in a personal computer (PC) has been changed to a more efficient one based on a fixed-point scheme, reducing system memory variable usage and leading to an increase in computation speed. The results show that the modifications proposed produced a clear increase in computation speed in comparison with the standard PC-based implementation, demonstrating the usefulness of the intrinsic parallelism of FPGAs in neurocomputational tasks and the suitability of both implementations of the algorithm for its application to the real world problems.

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Section: Fpga Implementation Of the Bp Algorithmmentioning

confidence: 99%

Efficient Implementation of the Backpropagation Algorithm in FPGAs and Microcontrollers

Ortega-Zamorano

Jerez

Munoz

et al. 2016

IEEE Trans. Neural Netw. Learning Syst.

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“…Distributed arithmetic generally represents a family of algorithms that use for calculation of sum of products or inner product or multiply and accumulate (MAC) Look-Up Tables [1]. Linear convolution can be formulated as a sum of products …”

Section: A Distributed Arithmetic Techniquementioning

confidence: 99%

High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA

Fiala

Linhart

2014

2014 International Conference on Applied Electronics

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Digital filters are necessary in digital transmitter / receiver side and popularity of Software Defined Radio (SDR) is forcing complex digital signal processing blocks to be implemented in parallel design flow on FPGA or ASIC. The goal of this paper is to develop efficient pipelined polyphase FIR filter structures in VHDL language for RTL synthesis on FPGA. The proposed structures contain fully parallel polyphase decimation and interpolation FIR filter models. The first part of this paper is focused on formulation of distributed arithmetic technique with polyphase decomposition, which represents the core of designed models. The second part describes mentioned polyphase FIR VHDL models. The extensive emphasis will be put on efficient pipelined implementation with excellent registered performance and optimal design size balance. The third part of this paper deals with rapid design and simulation of proposed VHDL models. The result of RTL synthesis is finally discussed. Very good performance and optimal design size are main benefits of proposed polyphase FIR filters. Developed structures are very suitable for multichannel operation in digital I/Q receiver.

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“…Though analog chip designs used to be implemented on smaller die sizes, but currently, with the noise associated with modern sub-micrometer circuits, digital systems are often much more densely integrated than analog designs and this has been yielded to a compact, low-power, and low-cost designs [1]. DSP (digital signal processing) as a subfield of signal processing is used in numerous applications such as most of associated threads in disparate fields of image processing, audio and speech signal processing, digital communications, biomedicine, etc.…”

Section: Introductionmentioning

confidence: 99%

“…Developing both programmable DSP chips and dedicated system-on-chip (SoC) solutions has been an active area of development and research over the past three decades [2]. Three important factors which have undoubtedly affected digital signal processing are development of an efficient way of computing DFT in 60s [3], commercial production of programmable digital signal processors in which calculation of fixed point arithmetic operations in one clock cycle became possible [1], and, finally introduction of modern FPGAs which provides low cost and fast DSP arithmetic implementation using a semi-ASIC architecture.…”

Section: Introductionmentioning

confidence: 99%

A Low Cost High Speed FPGA-Based Image Processing Framework

Mahmoodi

Sayedi

2016

IJMECS

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Abstract-In this paper, a high-speed and low-cost image processing framework based on MATLAB-FPGA interface is proposed that can be used in researches aiming at developing wide variety of not only image processing tasks but also many signal processing applications. In addition, this new framework could be exploited for several other tasks such as on-chip verification, using PC as an enormous external RAM for FPGA while preserving high speed data access, developing hardware-software co-designs, etc. The communication between FPGA and MATLAB is via 1Gbs Ethernet based on UDP/IP protocol which is very promising for high speed data transmission in point-topoint communications. UDP stack is efficiently designed in FPGA based on a fully pipelined architecture with minimum level of logic in order to reach high performance.. Dynamic data transmission between the UDP stack, memory and an arbitrary image processing module makes it possible to practically simulate, debug and implement most relevant applications. The hardware system is relatively low-cost and it consumes a negligible area of a Spartan-6 LXT45 Xilinx FPGA. Operating at 1 Gb/s, theoretically, the system is capable of processing 132 frames of 640*480 color images in a second. The effectiveness of the system is evaluated by means of both place and route simulation and practical implementation of a skin detection algorithm and a motion detector.

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Digital Signal Processing with Field Programmable Gate Arrays

Abstract: Page 123 Table 2.11, m=1: Replace "YK=K1 (X0 cos(Z0)+Y0sin(Z0))" with "YK=K1 (Y0 cos(Z0)+X0sin(Z0))" Page 123 Table 2.11, m=-1: Replace "XK=K-1√X0 2 + Y0 2 " with "XK=K-1√X0 2-Y0 2 " Replace "YK=K-1 (X0 cosh(Z0)+Y0sinh(Z0))" with "YK=K-1 (Y0 cosh(Z0)+X0sinh(Z0)

Cited by 78 publications

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Efficient Implementation of the Backpropagation Algorithm in FPGAs and Microcontrollers

Efficient Implementation of the Backpropagation Algorithm in FPGAs and Microcontrollers

High performance polyphase FIR filter structures in VHDL language for Software Defined Radio based on FPGA

A Low Cost High Speed FPGA-Based Image Processing Framework

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