Digital signal multi-processor for matrix applications

Mom

“…There is a large body of research on array multiprocessors, some of which made it into products for the high-end supercom-puter market [18] and there is also current research looking in matrix-based ISAs to be used in floating point applications [19]. The key difference between these previous proposals and MOM is that, in the context of floatingpoint engineering-like applications, a matrix ISAs is not that much of an advantage over a traditional vector ISA.…”

Reduced latency IEEE floating-point standard adder architectures

“…The adder was functionally verified against the Berkeley IEEE-754 test vector set and sets of random vectors generated by a golden device (SUN UltraSPARC 60 [5]). This FP adder will be used in a parallel processor node [1] for fast matrix computations. …”

“…FP adders must be fast to match the increasing clock rates demanded by deep submicron technologies with a small number of pipelining stages to minimise latency and improve branch resolution time. FP adders must also be small, particularly for use in parallel processing systems [1,11] with multiple FP units (FPUs).…”

“…This paper discusses the design and implementation of an IEEE-754 compliant double precision 3-cycle floatingpoint adder which uses minimal hardware for use in a parallel processor with multiple FPUs [1]. This is achieved by merging the rounding stage with the significand addition by using a flagged prefix adder [2] which provides an "instant" plus "1" or plus "2" of the significand result for a small increase (one complex gate plus a half adder delay) in critical path length with much less hardware than two adders or one compound adder.…”