2014
DOI: 10.1117/12.2057519
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Digital pixel CMOS focal plane array with on-chip multiply accumulate units for low-latency image processing

Abstract: A digital pixel CMOS focal plane array has been developed to enable low latency implementations of image processing systems such as centroid trackers, Shack-Hartman wavefront sensors, and Fitts correlation trackers through the use of in-pixel digital signal processing (DSP) and generic parallel pipelined multiply accumulate (MAC) units. Light intensity digitization occurs at the pixel level, enabling in-pixel DSP and noiseless data transfer from the pixel array to the peripheral processing units. The pipelined… Show more

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Cited by 2 publications
(2 citation statements)
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“…21 SWIR-PPI is hybridized to a COTS InGaAs detector array via indium bump bonding. Each pixel in the DROIC includes a sigma-delta ADC capable of recording up to 28 bits of inpixel digital output.…”
Section: Infrared Computational Imaging Arraymentioning
confidence: 99%
“…21 SWIR-PPI is hybridized to a COTS InGaAs detector array via indium bump bonding. Each pixel in the DROIC includes a sigma-delta ADC capable of recording up to 28 bits of inpixel digital output.…”
Section: Infrared Computational Imaging Arraymentioning
confidence: 99%
“…[12][13][14][15][16][17] We have previously shown the utility of MIT LL focal plane arrays for high-speed transient imaging of hyper-temporal targets by leveraging inpixel flutter shutter capabilities combined with on-chip processing. [18][19][20] Our PETEI testbed combines dynamic optical encoding at the pupil plane with novel focal plane array on-chip and per-pixel flutter shutter to realize image plane coding with no mechanical moving parts. PETEI is used to realize applications such as passive 3D ranging, pixel superresolution, and extended depth of focus with the addition of a compressive sensing framework.…”
Section: Introductionmentioning
confidence: 99%