Digital filtering in FPGAs

Mintzer, L.

doi:10.1109/acssc.1994.471682

Cited by 14 publications

(4 citation statements)

References 1 publication

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“…DA structure is very suitable to be implemented on FPGAs. In fact, DA-structured, FPGA-based digital filters have become a very successful contender in digital filtering applications (White 1989, Mintzer 1995.…”

Section: Distributed Arithmeticmentioning

confidence: 99%

Distributed arithmetic implementation of multivariable controllers for smart structural systems

Yuan

Sana

Pottinger

et al. 2000

Smart Mater. Struct.

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Smart structural systems require the electronic control systems which are integrated into the structures to be small, light weight and power-efficient. The field programmable gate array (FPGA) is a good platform to implement such controllers. In our previous work, FPGA-based digital controllers were built and tested on a simple structural system. In order to implement multivariable controllers, the hardware resources for FPGA-based architecture need to be further reduced. Distributed arithmetic (DA) has long been proven to be a very efficient means to mechanize computations that are dominated by inner products involving constant multiplicand. The computational requirements of the smart structural controllers match this type very well. In this paper various DA structure controllers are designed and results are compared with multiply-and-accumulate structure controllers. Single-and multi-variable controllers are implemented and tested on a cantilevered beam.

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Section: Distributed Arithmeticmentioning

confidence: 99%

Distributed arithmetic implementation of multivariable controllers for smart structural systems

Yuan

Sana

Pottinger

et al. 2000

Smart Mater. Struct.

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“…From these two new matrices, W o (n × n) and W c (n × n), can be found termed the observability and controllability Gramians respectively which are given in equations ( 17) and (18). The ith diagonal element of the controllability Gramian and the observability Gramian represents the total energy in the ith unit pulse state response and output response respectively.…”

Section: Global Sensitivity Index Upper Boundmentioning

confidence: 99%

Design and implementation of digital controllers for smart structures using field programmable gate arrays

Kelly¹,

Rao²,

Pottinger³

et al. 1997

Smart Mater. Struct.

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Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the smart patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. Field programmable gate arrays (FPGA) are specifically targeted as a hardware platform because these devices are highly flexible, power efficient, and reprogrammable.The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation. MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language (VHDL). These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them; simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using FPGA hardware. The experimental closed loop response is gathered for an automated FPGA controller implementation. Finally, the integration of FPGA based controllers into a multi-chip module (MCM) is explored, which represents the next step towards the realization of the smart patch.

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“…In this study, we map three image-processing kernels from the OpenCV library to an Altera Stratix-V FPGA on a variety of RC platforms. The Sobel [2] and Canny [3] kernels are used for edge detection, while the Speeded-Up Robust Features (SURF) [4] kernel is used for feature extraction. These information-extraction kernels represent the initial stage of many image-processing applications.…”

Section: Introductionmentioning

confidence: 99%

Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA

Hill

Craciun

George

et al. 2015

2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors (ASAP)

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Application development with hardware description languages (HDLs) such as VHDL or Verilog involves numerous productivity challenges, limiting the potential impact of reconfigurable computing (RC) with FPGAs in highperformance computing. Major challenges with HDL design include steep learning curves, large and complex codes, long compilation times, and lack of development standards across platforms. A relative newcomer to RC, the Open Computing Language (OpenCL) reduces productivity hurdles by providing a platform-independent, C-based programming language. In this study, we conduct a performance and productivity comparison between three image-processing kernels (Canny edge detector, Sobel filter, and SURF feature-extractor) developed using Altera's SDK for OpenCL and traditional VHDL. Our results show that VHDL designs achieved a more efficient use of resources (59% to 70% less logic), however, both OpenCL and VHDL designs resulted in similar timing constraints (255MHz < fmax < 325MHz). Furthermore, we observed a 6× increase in productivity when using OpenCL development tools, as well as the ability to efficiently port the same OpenCL designs without change to three different RC platforms, with similar performance in terms of frequency and resource utilization.

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Digital filtering in FPGAs

Cited by 14 publications

References 1 publication

Distributed arithmetic implementation of multivariable controllers for smart structural systems

Distributed arithmetic implementation of multivariable controllers for smart structural systems

Design and implementation of digital controllers for smart structures using field programmable gate arrays

Comparative analysis of OpenCL vs. HDL with image-processing kernels on Stratix-V FPGA

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