Digital Defect-Oriented Test Methodology for Flipped Voltage Follower Low Dropout (LDO) Voltage Regulators

Saikiran, Marampally; Ganji, Mona; Chen, Degang

doi:10.1109/sbcci55532.2022.9893243

Cited by 6 publications

(8 citation statements)

References 22 publications

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“…As IOI method is already explained in detail in previous section, we discuss the method for LDOs briefly in this subsection. For more insight into the testing method, the readers of this paper are encouraged to refer to [18]. In this testing method, either a positive or negative offset is injected into the error amplifier by using the testing transistors 𝑀 𝑃𝑇 , 𝑀 𝑁𝑇 .…”

Section: Intentional Offset Injection Methods -Fvf Ldomentioning

confidence: 99%

“…Once these offsets are injected, the defects are tested by checking the defect truth table presented in Table 5. There are four dual threshold detectors [18] placed at fault-sensitive nodes (𝑉 𝑂𝑈𝑇_𝐿𝐷𝑂 , 𝑉 𝑂𝑈𝑇_𝐸𝐴 , 𝑉 𝑋 , 𝑉 𝐺_𝑀𝑃 ) and are named (𝐷𝐸𝑇_𝐸𝐴_𝑂𝑈𝑇, 𝐷𝐸𝑇_𝐿𝐷𝑂_𝑂𝑈𝑇 , 𝐷𝐸𝑇_𝑉𝑋 , 𝐷𝐸𝑇_𝑉𝐺_𝑀𝑃) as shown in Fig. 13.…”

Section: Intentional Offset Injection Methods -Fvf Ldomentioning

confidence: 99%

“…18, some defects are detected, and some are not detected. Similar to op amp case, after removing the redundant defects such as diode-connections and cascode defects as explained in [18], the overall defect coverage is 94%. Table 6 gives a performance comparison for IOI based defect simulation of FVF LDO between conventional framework and the proposed framework.…”

Section: Defect Detection Of Operational Amplifier Using Ioi With Pro...mentioning

confidence: 96%

“…Similar to the testing of operational amplifier, we test the defects in the FVF LDO using two similar methods. The first method is predominantly a DC testing method known as intentional offset injection (IOI) method for LDOs proposed in [17], [18] and the second testing method is the Oscillation Test Method (OTM) [15], [16].…”

Section: Defect Simulation: Fvf Low Drop-out Regulatormentioning

confidence: 99%

“…The FVF LDO that is used in this work is shown in Fig. 13 and is similar to the architecture presented in [18], [21]. Our LDO has a bias block, an error amplifier (EA) and a power stage.…”

Section: Circuit Under Test: Fvf Ldomentioning

confidence: 99%

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Low-Cost Defect Simulation Framework for Analog and Mixed Signal (AMS) Circuits with Enhanced Time-Efficiency

Saikiran

Sekyere

Ganji

et al. 2022

Preprint

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Defect-oriented testing is becoming increasingly popular in recent times, especially in safety-critical applications in automotive, space and medical industries. The stringent quality requirements from these industries such as zero defective parts per million (DPPM) necessities a need to have efficient defect testing methods. Furthermore, the overall development time of integrated circuit can be reduced by reducing the defect simulation time. In this work, we present a simple and time-efficient defect simulation framework for pre-silicon testing of AMS circuits. In our method, a given defect model is realized using Verilog-A modules and tests multiple defects in a circuit in a single-run simulation. In contrast to the conventional defect simulation framework, our method saves simulation time by avoiding the repetitive work of generating a netlist for each defect and by reducing the time overhead for the simulator to interface with data/file-handling system. To strongly validate our proposed framework, we use diverse AMS circuits such as operational amplifier (op amp), fast transient flipped-voltage follower based low-dropout regulator (FVF LDO) and Successive-approximation-register (SAR) analog-to-digital converters (ADC). For DC testing schemes used for op amp and LDO testing, we show that our proposed framework reduces the simulation time to less than one-tenth (1/10th) in comparison with conventional framework. On the other hand, for the transient testing scheme, the proposed framework reduces the simulation time to less than 50% of the conventional framework. Furthermore, we also show that there is no negative impact on the defect coverage using the proposed framework.

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Section: Intentional Offset Injection Methods -Fvf Ldomentioning

confidence: 99%

Section: Intentional Offset Injection Methods -Fvf Ldomentioning

confidence: 99%

Section: Defect Detection Of Operational Amplifier Using Ioi With Pro...mentioning

confidence: 96%

Section: Defect Simulation: Fvf Low Drop-out Regulatormentioning

confidence: 99%

“…The FVF LDO that is used in this work is shown in Fig. 13 and is similar to the architecture presented in [18], [21]. Our LDO has a bias block, an error amplifier (EA) and a power stage.…”

Section: Circuit Under Test: Fvf Ldomentioning

confidence: 99%

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