Digital circuits verification with consideration of destabilizing factors

Goldman, Rich; Melikyan, Vazgen; Babayan, E.

doi:10.1109/idt.2011.6123109

Cited by 1 publication

(1 citation statement)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…A system development life cycle (SDLC) method was presented [13] for the asynchronous circuit verification, the method can be used to describe the desired asynchronous circuit behaviors and refine those descriptions. The verification approach of digital circuits by using a lot of internal and external destabilizing factors was investigated [14], the destabilizing factors impact on the circuit operations was considered when the verification was carried out. The verification of the nano CMOS circuit was discussed [15], and a gate model was given by using a simplified transistor model.…”

Section: Introductionmentioning

confidence: 99%

Determining Equivalent Signal Lines by Weight Value Assignment for Logic Verification of Digital Circuits

Zhang

Ling²,

Chen³

2014

TOEEJ

View full text Add to dashboard Cite

Abstract:The VLSI technology has led to the increased complexity in hardward design, therefore the verification for the correctness of circuit operations has become an exrtremely important task. The verification procedure can be reduced by means of the equivalent signal lines in the circuits. In this paper, a new method is presented for determining the equivalent signal lines, the method utilizes the weight value assignment of signal lines in circuits. First of all, the method makes use of the topological information of circuits to perform forward weight value assignments, assign weight values to the signal lines from the primary inputs to primary outputs. Afterwards, carry out the backward weight value assignment, assign weight values to the signal lines from the primary outputs to primary inputs. Secondly, carry out the random pattern simulation to further check the equivalence of signal lines. A lot of experimental results show that the verification of digital circuits can be carried out effectively by using the method proposed in this paper, the time being needed for the verification procedure can be cut down by utilizing the equivalent signal lines.

show abstract

Section: Introductionmentioning

confidence: 99%