Digital circuit design for minimum transient energy and a linear programming method

Abstract

This paper provides a theoretical basis for eliminating or reducing the energy consumption due to transients in a synchronous digital circuit. The transient energy is minimized when every gate has no more than one output transition per clock cycle. This condition is achieved for a gate when the gate delay equals or exceeds the maximum di erence between path delays at gate inputs. In practice, path delays are adjusted either by increasing gate delays or by inserting delay bu ers. The minimum transient energy design is obtained when no delay bu er is added. This design requires possible increases in gate delays to meet the minimum energy condition at all gates. However, the delay of the critical path may be increased. In an alternative design, where the critical path delay is not allowed to increase, delay bu ers may have to be added. The theory in this paper allows trade-o s between minimum transient energy and critical path delay. We formulate the problem as a linear program to obtain the minimum transient energy design with the smallest number of delay bu ers for a given overall delay of the circuit. An optimized four-bit ALU circuit is found to consume 53 peak and 73 average power compared t o the original circuit.

Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations

“…Proof: We derive the two upper bounds for maximum transition and take the lower of those as a tighter upper bound. This analysis is an improvement over a previously reported result [1].…”

“…This bound is 0 or 1 depending upon whether the output values before and after transients, i.e., IV and F V , are same or different. This has been used as the condition for minimum glitch power design [1]. When there are split ambiguity intervals, we can obtain a tighter lower bound.…”

Input-specific Dynamic Power Optimization for VLSI Circuits

“…Agrawal et al [2] combined path balancing and hazard filtering in their LP model to determine the delay assignment for each gate. In subsequent work, their group proposed [8] an improvement reducing the complexity of the constraint set from exponential to linear in the circuit size.…”

“…In all the previous LP models [2,7,8], the glitch optimization of the circuit is considered under arbitrary gate inputs. The LP solution ensures the absence of a glitch for any input vector sequence and for all input signal combinations at all gates.…”

“…The principal idea in glitch reduction is to find delay assignment for all gates in the circuit to reduce the differential path delays at gate inputs with respect to the inertial delays. Optimization techniques for glitch reduction are the balanced delay [5] and hazard filtering [1] methods, implemented through a variety of algorithms such as transistor sizing [12,14], gate sizing [3,6], and linear programming [2,7,8].…”