Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Storace, Marco; Poggi, Tomaso

doi:10.1002/cta.610

Cited by 53 publications

(70 citation statements)

References 69 publications

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“…Once the FIFO blocks are full, the computation of the estimated output is performed by the PWAS_i ( 1, … , ) blocks, which are responsible for the evaluation of the PWAS functions. A detailed description of these blocks is available in [11]. Each PWAS_i block communicates the end of its computation with a ready_i signal; as soon as all ready_i signals are active, the results of each function evaluation (fpwas_i) are added up by an adder block, which provides the estimation of the unmeasurable output , and a global ready signal is set to logic value '1' indicating that the result is available.…”

Section: Virtual Sensor Architecturementioning

confidence: 99%

Estimation of stepping motor current from long distances through cable-length-adaptive piecewise affine virtual sensor

et al. 2015

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<p>In this paper a piecewise affine virtual sensor is used for the estimation of the motor-side current of hybrid stepper motors, which actuate the LHC (Large Hadron Collider) collimators at CERN. The estimation is performed starting from measurements of the current in the driver, which is connected to the motor by a long cable (up to 720 m). The measured current is therefore affected by noise and ringing phenomena. The proposed method does not require a model of the cable, since it is only based on measured data and can be used with cables of different length. A circuit architecture suitable for FPGA implementation has been designed and the effects of fixed point representation of data are analyzed.</p>

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Section: Virtual Sensor Architecturementioning

confidence: 99%

Estimation of stepping motor current from long distances through cable-length-adaptive piecewise affine virtual sensor

et al. 2015

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“…Several digital architectures have been reported in the literature implementing this approach [9]- [11]. They consist of a memory that stores the values of the function at the simplex vertices, a block to find the simplex within the hyper- rectangular that the point belongs to (finding the hyperrectangular is an easy task), and a multiply-accumulate or a weighted sum block that calculates the affine expression for the output (in serial or parallel, respectively).…”

Section: B Simplicial Pwa Architecturementioning

confidence: 99%

“…The time needed to calculate the value of the function at a given input point can be 1 clock period (in the case of a fully parallel architecture) or grows as [log 2 m+n]*T CK (in the case of a serial architecture) [11].…”

Section: B Simplicial Pwa Architecturementioning

confidence: 99%

Digital implementation of hierarchical piecewise-affine controllers

Baturone

Martínez-Rodríguez

Brox

et al. 2011

2011 IEEE International Symposium on Industrial Electronics

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Abstract-This paper proposes the design of hierarchical piecewise-affine (PWA) controllers to alleviate the processing time or prohibitive memory requirements of large controller structures. The constituent PWA modules of the hierarchical solution have fewer inputs and/or coarser partitions, so that they can reduce considerably the hardware resources required and/or the time response of the controller. A design methodology aided by CAD tools is employed to design the parameters of the controller, implement its architecture in an FPGA, and verify the static and dynamic behavior of the digital implementation by applying hardware-in-the-loop testing.

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“…1a) [7], [18], [21]; they are simplexes if the partition is simplicial (Fig. 1b) [19], [23], [24]; and they are hyper-rectangles if the partition is hyper-rectangular (Fig. 1c) [22].…”

Section: Introductionmentioning

confidence: 99%

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

Martínez-Rodríguez

Brox

Baturone

2015

IEEE Trans. Contr. Syst. Technol.

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Abstract-This paper presents a small, fast, low power consumption solution for piecewise-affine (PWA) controllers. To achieve this goal, a digital architecture for Very Large Scale Integration (VLSI) circuits is proposed. The implementation is based on the simplest lattice form, which eliminates the point location problem of other PWA representations and is able to provide continuous PWA controllers defined over generic partitions of the input domain. The architecture is parameterized in terms of number of inputs, outputs, signal resolution, and features of the controller to be generated. The design flows for Field Programmable Gate Arrays (FPGAs) and Application Specific Integrated Circuits (ASICs) are detailed. Several application examples of explicit model predictive controllers (such as an adaptive cruise control and the control of a buck-boost DC-DC converter) are included to illustrate the performance of the VLSI solution obtained with the proposed latticebased architecture.

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Digital architectures realizing piecewise‐linear multivariate functions: Two FPGA implementations

Cited by 53 publications

References 69 publications

Estimation of stepping motor current from long distances through cable-length-adaptive piecewise affine virtual sensor

Estimation of stepping motor current from long distances through cable-length-adaptive piecewise affine virtual sensor

Digital implementation of hierarchical piecewise-affine controllers

Digital VLSI Implementation of Piecewise-Affine Controllers Based on Lattice Approach

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