Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

Sakuma, Katsuyuki; Smith, K L; Tunga, Krishna; Perfecto, Eric; Wassick, Thomas; Pompeo, Frank; Nah, Jae-Woong

doi:10.1109/ectc.2012.6248866

Cited by 19 publications

(4 citation statements)

References 9 publications

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Section: Introductionmentioning

confidence: 99%

“…Much work has been done to mitigate CPI stress and resulting WBs by improving adhesion and fracture toughness of dielectric films [8], improving the via passivation design [5], developing a low CTE organic substrate [9], improving the chip joining process (slow cooling rate post-reflow) [6], developing differential heating/cooling chip joining method [7]. CPI Stresses in the BEOL can be further reduced by using an epoxy compound as an underfill (encapsulation) material for C4s in a flip chip package which helps redistribute and thus mitigate the stress in the C4s.…”

Section: Introductionmentioning

confidence: 99%

“…White Bumps are the prime indicator of localized cracks or delamination in the dielectric layers in an organic laminate-based electronic package. This failure mode is sensitive to the structure at the BEOL, bump dimension, dielectric material properties (adhesion and fracture toughness), die fabricating process, CTE mismatch between the die and the substrate, and cooling rate during chip joint [2][3][4][5][6][7].The use of Ultra-Low K (ULK) dielectric material in BEOL for advanced circuitry design posts a significant challenge to chip packaging reliability since the ULK film material is weak in both adhesion and fracture toughness versus conventional dielectric materials. Much work has been done to mitigate CPI stress and resulting WBs by improving adhesion and fracture toughness of dielectric films [8], improving the via passivation design [5], developing a low CTE organic substrate [9], improving the chip joining process (slow cooling rate post-reflow) [6], developing differential heating/cooling chip joining method [7].…”

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Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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Chip-Package Interaction (CPI) related failure risk has increased in organic laminate-based electronic packages fueled in part by certain industry-segments' requirements for larger silicon die size and signal performance. CPI-related stresses increase directly with radial distance from the center of the die, known as distance from the neutral-point (DNP). The resulting risk of local delamination (White Bumps, WBs) in the silicon back-end-of-line (BEOL), fracture of C4 interconnections and failure of underfill and chip ultimately impact electronic package reliability. Named from the notable visible white halo or circle around a C4 in a CSAM (C-Mode Scanning Acoustic Microscopy) image, WBs are the prime indicator of a CPI-related failure event in an organic laminatebased electronic package.Laminate and BEOL design, specifically wiring proximal to the C4 interconnection, are known to influence WB reliability. In this paper we specifically study the effect of laminate and BEOL design on the generation of white bumps. Four different chip designs, some of which are more susceptible to WBs than others are mated with both productdesign and "flat" laminates, or laminates consisting of only a core and single copper layer on each side. Our ultimate goal is to highlight the silicon & laminate designs' ability to modulate WB occurrences, to create design ground-rules thereby relaxing the cost and facilitating the development of package assembly solutions.A comprehensive experiment was carried out to achieve these goals. As companion test vehicles to product laminates, four different flat laminate (0-2-0) designs were fabricated with several different core materials to both segregate the effect of laminate wiring design and modulate the overall laminate coefficient of thermal expansion (CTE). Four separate chip designs were used to study the effect of the back end of line design.Thermal stress was induced in the experiment using a high-cooling rate or "hammer" chip-join (HCJ) reflow profile which drives a higher C4 shearing stress than with the nominal profile. The occurrence of WBs was then monitored while the test vehicles were repeatedly subjected to the hammer profile in a controlled hammer thermal cycling (HTC) process. Diagnostic measurements including 3D Surface Metrology and CSAM were performed after each HTC cycle to monitor both laminate warpage and WB occurrence respectively. White Bump evolution was statistically analyzed and correlated to each die design, laminate cross-sectional design and CTE. Results demonstrated the importance of laminate design in that the flat laminates consistently lead to fewer WBs than product laminates. Lower-CTE laminates also result in fewer WBs than product laminates. IntroductionChip-package interaction thermo-mechanical stresses (CPI Stress) exist in electronic packages due to the coefficient of thermal expansion mismatch among the different materials used to fabricate the package and critical temperatures (curing) at which these materials are processed. Such stresses can reach th...

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

mentioning

confidence: 99%

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Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Pan

Zitz

Questad

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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“…Although throughput is slower compared to furnace reflow, TC bonding can achieve fine-pitch bonding of warped components as it features placement accuracy of about ±2 µm. Also, C4 stresses and chip warpage can be reduced by differential heating/cooling chip join process using TC bonding [9]. In this paper, the bonding challenges for large die packaging are discussed.…”

Section: Introductionmentioning

confidence: 99%

Bonding technologies for chip level and wafer level 3D integration

Sakuma

Skordas

Zitz

et al. 2014

2014 IEEE 64th Electronic Components and Technology Conference (ECTC)

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This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm 2 . Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 µm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

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Delamination and Reliability Issues in Packaged Devices

Lei

Kumar

2014

Adhesion in Microelectronics

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Differential heating/cooling chip joining method to prevent chip package interaction issue in large die with ultra low-k technology

Cited by 19 publications

References 9 publications

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Chip Package Interaction: An Experiment Study on White Bump Mitigation Using Flat Laminates

Bonding technologies for chip level and wafer level 3D integration

Delamination and Reliability Issues in Packaged Devices

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