Differential Electromagnetic Attack on an FPGA Implementation of Elliptic Curve Cryptosystems

Mulder, Elke De; Örs, Berna; Preneel, Bart; Verbauwhede, Ingrid

doi:10.1109/wac.2006.375739

Cited by 24 publications

(20 citation statements)

References 12 publications

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“…From the view point of the cryptographic hardware implementation, one of the main issues is related to the security of processed information by side-channel analysis (SCA) attacks. The SCA attacks, such as differential power analysis (DPA) [3] and differential electromagnetic analysis (DEMA) [4] have become a crucial challenge for cryptographers and hardware engineers to maintain the secrecy of private information in cryptographic hardware implementation, such as in smart card. The main factors of aforementioned attacks are related to CMOS logic power consumption, required operational time and the electromagnetic signals emanating from a device while it is executing a cryptographic process.…”

Section: Introductionmentioning

confidence: 99%

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Monteiro

Takahashi

Sekine

2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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This paper investigates the effectiveness of secure dual-rail adiabatic logic against power analysis attack under CMOS process variations. The ability of the previously proposed logic in multiplier over GF (2 4 ) is investigated in terms of transitional energy dissipation using 100 data samples from Monte Carlo simulation. The adiabatic multiplier circuits are simulated using 0.18-μm and 90-nm CMOS process at an operating power clock frequency of 12.5MHz. The SPICE simulation results show that the proposed CSSAL multiplier has high stability and strong immunity in consuming constant power than other investigated logic styles.

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Section: Introductionmentioning

confidence: 99%

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Monteiro

Takahashi

Sekine

2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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“…A DPA attack seeks to reveal the secret key of a smart card by statistically analyzing the power fluctuations that occur while the device encrypts and decrypts large blocks of data [1]. Apart from the DPA attacks, the differential electromagnetic radiation attack (DEMA) has been extensively studied [2]. DEMA attacks can reveal secret information because the current flow during the switching of the CMOS gates causes a variation in the surrounding electromagnetic field, which can be monitored by positioning an inductive probe around the microcontroller chip.…”

Section: Introductionmentioning

confidence: 99%

“…The idea behind HD model is to count the number of P 0→1 and P 1→0 , P 0→0 and P 1→1 transitions that occur in the digital circuit during a certain time interval with the assumption of (P 0→1 ≈ P 1→0 ) = (P 0→0 ≈ P 1→1 ). From the view point of DPA and DEMA attack techniques, the scCMOS and DR-CMOS are vulnerable, because they perform different peak current transition and different large magnitude which cause a sudden variation of the electromagnetic field surrounding the chip as reported in [2]. As a result, the DPA and DEMA attacks are a bit difficult to avoid.…”

Section: Introductionmentioning

confidence: 99%

Process variation verification of low-power secure CSSAL AES S-box circuit

Monteiro

Takahashi

Sekine

2014

2014 IEEE 57th International Midwest Symposium on Circuits and Systems (MWSCAS)

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In this work, we implement our previously proposed charge-sharing symmetric adiabatic logic (CSSAL) in an 8-bit S-box circuit using a multi-stage positive polarity Reed-Muller (PPRM) representation with a composite field technique. We evaluate the effectiveness of the CSSAL S-box circuit against side-channel attacks towards the variations of the CMOS process technology. The results of this paper are obtained from the SPICE simulation with 0.18-µm and 90-nm standard CMOS technology at an operating frequency band of 125 KHz-70 MHz.

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“…Therefore, the side-channel analysis (SCA) attacks were introduced in [4] have become crucial challenges for cryptographers and hardware engineers to maintain the secrecy of private information in the cryptographic hardware, such as in smart card. Among other types of side-channel attacks, differential power analysis (DPA) attacks [5] and differential electromagnetic analysis (DEMA) [6] have been taken into consideration because of their technical measurement and statistical calculation efficiency to find the secret key and the applicability on various types of implementation.…”

Section: Introductionmentioning

confidence: 99%

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

Monteiro¹,

Takahashi²,

Sekine³

2013

IJMO

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Abstract-The bit-parallel multiplier over Galois filed arithmetic algorithm and the circuit architecture have been widely studied and implemented in cryptosystem. In this paper, we implement the proposed secure and low-power dual-rail adiabatic logic circuit into the bit-parallel cellular multiplier over GF(2 4 ). The full custom design of the layout has been designed in cadence virtuoso IC6.1 with the chip size of 172×155 m 2 , and the post-layout cyclical power consumption of 14pJ at 12.5MHz using 0.18μm CMOS technology has achieved; while, the well-known conventional TDPL logic in our work using the same technology occupied 183×m 2 of the chip size and 123pJ per cycle. The thoroughly investigation results define that our proposed logic improve energy reduction and the circuit immunity to side-channel attack in the low frequency application, whereas, the TDPL shows the better security performance at high frequency range.Index Terms-Bit-parallel multiplier, adiabatic, low-power, side channel attack, cryptography.

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Differential Electromagnetic Attack on an FPGA Implementation of Elliptic Curve Cryptosystems

Cited by 24 publications

References 12 publications

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation

Process variation verification of low-power secure CSSAL AES S-box circuit

Low Power Bit-Parallel Cellular Multiplier Implemetation in Secure Dual-Rail Adiabatic Logic

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