Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Alnuayri, Turki; Khursheed, Saqib; Martinez, Antonio Leonel Hernandez; Rossi, Daniele

doi:10.1109/tvlsi.2021.3115247

“…The DFF's typical structure is shown in Figure 1. A clock signal enables the clocked inverters and observe the corresponding output and not enabled state is assumed as a high impedance state [17]. Some flipflops have an option to specify their initial state through a configuration or initialization signal.…”

Section: Ff Power-up Statementioning

confidence: 99%

An efficient unused integrated circuits detection algorithm for parallel scan architecture

Sathyanarayana,

Kanathur Ramaswamy,

Srikantaswamy

et al. 2024

IJECE

1

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In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm.

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“…Oscillators are important building blocks of analog and digital systems. A ring oscillator (ROSC) is commonly used for generating sinusoidal signals for various applications such as true random number generator [1], current to voltage converter for temperature sensor [2], aging sensor [3], analog and digital converters [4], [5], phase-locked loop [6], for calibrating baseline interconnect path [7]. A ROSC is preferred because it has a robust and compact design and a wide tuning range.…”

Section: Introductionmentioning

confidence: 99%

A Differential Delay Cell for Ring Oscillators

Singh¹,

SINGH²,

Sakare³

2023

Preprint

0

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<p>This paper presents a differential delay cell (DDC) for a 3-stage current-starved ring voltage-controlled oscillator (CSRVCO). In the proposed delay cell, pass transistors and a pair of back-to-back transistors are connected in a symmetric structure that helps get less jittery output by providing similar charging and discharging paths from the load capacitor. The current flows from similar paths with the same type and number of transistors in the proposed DDC-based CSRVCO. For verifying the DDC operation, the 3-stage CSRVCO using the proposed DDC is implemented with a standard 65nm CMOS technology with 1V supply. Post-layout simulation results confirm the correct operation of the proposed DDC using the CSRVCO with minimal jitter at the output. The proposed CSRVCO can be tuned from 0.88 GHz to 2.76 GHz. The phase noise of -94.54 dBc Hz was measured at 1MHz offset frequency for the center frequency of 2.76 GHz. The CSRVCO was designed using the proposed DDC occupied area 1198.43 μm2, and dissipated power is 5.19mW.</p>

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“…Free-running ROSCs are used in some applications [1], [3]. In most of the applications, tuning of frequency is required [2], [4]- [10].…”

Section: Introductionmentioning

confidence: 99%

A Differential Delay Cell for Ring Oscillators

Singh¹,

SINGH²,

Sakare³

2023

Preprint

0

View full text Add to dashboard Cite

<p>This paper presents a differential delay cell (DDC) for a 3-stage current-starved ring voltage-controlled oscillator (CSRVCO). In the proposed delay cell, pass transistors and a pair of back-to-back transistors are connected in a symmetric structure that helps get less jittery output by providing similar charging and discharging paths from the load capacitor. The current flows from similar paths with the same type and number of transistors in the proposed DDC-based CSRVCO. For verifying the DDC operation, the 3-stage CSRVCO using the proposed DDC is implemented with a standard 65nm CMOS technology with 1V supply. Post-layout simulation results confirm the correct operation of the proposed DDC using the CSRVCO with minimal jitter at the output. The proposed CSRVCO can be tuned from 0.88 GHz to 2.76 GHz. The phase noise of -94.54 dBc Hz was measured at 1MHz offset frequency for the center frequency of 2.76 GHz. The CSRVCO was designed using the proposed DDC occupied area 1198.43 μm2, and dissipated power is 5.19mW.</p>

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Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

Cited by 11 publications

References 28 publications

An efficient unused integrated circuits detection algorithm for parallel scan architecture

An efficient unused integrated circuits detection algorithm for parallel scan architecture

A Differential Delay Cell for Ring Oscillators

A Differential Delay Cell for Ring Oscillators

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