Dielectric Separated Independent Gates Junctionless Transistor (DSIG-JLT) For Highly Scaled Digital Logic Implementation

Garg, Neha; Pratap, Yogesh; Gupta, Mridula; Kabra, Sneha

doi:10.1109/tnano.2021.3066814

Cited by 3 publications

(3 citation statements)

References 29 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The hierarchical design of a signal processing block consists of sub-systems such as multipliers and adders that form the fundamental building block for any signal processing unit. In this chapter, a literature review on the design and analysis of various multipliers and adders is presented [8][9][10]. The adder function is used in the majority of applications.…”

Section: Literature Surveymentioning

confidence: 99%

“…Adder was a significant source in applications such as laptops, personal computers (PC), microprocessors, microcontrollers, filters, etc. As a result, the creation of low-power and area-efficient adders plays a critical role in modern technologies [10][11][12][13]. The pull-up network employs two PMOS transistors, whereas the pull-down network employs two NMOS transistors.…”

Section: Literature Surveymentioning

confidence: 99%

See 1 more Smart Citation

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

View full text Add to dashboard Cite

This research focuses on critical hardware components of an Internet of Things (IoT) system for reconfigurable processing systems. Single-Instruction Multiple-Data (SIMD) processors have recently been utilized to preprocess data at energy-constrained sensor nodes or IoT gateways, saving significant energy and bandwidth for transmission. Using traditional CPU-based systems to implement machine learning algorithms is inefficient in terms of energy consumption. In the proposed method Single-Instruction Multiple-Data (SIMD) processors are assembled by scaling the largest possible operand value subunits into direct access to the internal memory, where the carry output of each unit is conditionally fed into the next unit based on the implementation of the SIMD Processor design for Internet of Things applications. Each method has evaluated sub-operations that contribute considerably to the overall potential of the design. If the single register file can complete the intended action, a zero (one)-signal is applied to each unit's carry input. Multiplexers combine two or more adders, sending the carry signal from one unit into another if additional units are necessary to compute the sum. The outcome results compare high-speed end device techniques in terms of area and power consumption. The proposed SIMD processor-based IoT healthcare monitoring system with a MIMD processor's performance analysis of comparison clearly demonstrates that the system produces decent outcomes. The suggested system has an area overhead of 85 m 2 , a power usage of 4.10 W, and a time delay of 20 ns.

show abstract

Section: Literature Surveymentioning

confidence: 99%

Section: Literature Surveymentioning

confidence: 99%

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

2024

Teh. vjesn.

View full text Add to dashboard Cite

show abstract

“…ONSIDERING that the industry seeks to miniaturization of CMOS transistors, research has increased on the design of transistors that reduce leakage current and have a significant switching speed in small dimensions [1]. The purpose of the fabrication of transistors with small dimensions is to be used in low-power digital circuits [2]- [3]. Therefore, two factors are very important in the design of a reliable transistor.…”

Section: Introductionmentioning

confidence: 99%

Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet

Bavir

Abbasi

Orouji

2022

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

In this paper, after calibrating the models and parameters used in the simulations based on experimental data, by using the opposite doping in the channel and between the gates in an asymmetric double-gate junctionless (JL) transistor with the 3nm gate length, a charge sheet (CS) was created. The results showed that, due to creating CS in the middle of the channel, the horizontal electric field was increased, thus more major carriers were depleted from the middle of the channel. With the analysis of the IDS-VGS diagrams at different temperatures, it was concluded that in the CS JL MOSFET, while the ON-state current is very close to compared that in the JL MOSFET (same structure without CS), the drain leakage current has decreased by around 10 3 . Furthermore, the IDS-VDS diagram showed that the drain current in the CS JL MOSFET was much less affected by the drain voltage compared to that in the JL MOSFET. Also in AC analysis and at 1MHz frequency, by using CS the parasitic capacitances were reduced. Due to the improvement obtained in the presence of the charge sheet, the proposed structure was used in designing an inverter. The results showed that in the presence of the charge sheet, logical high input range, and logical low input range were increased, and also, noise margin low (NML) and noise margin high (NMH) were improved.

show abstract

Impact of Channel Thickness on the Performance of JL-DG MOSFET based NAND, NOR, and NOT Logic Gates

Katharashala

Gandla

Bommineni

et al. 2022

2022 IEEE International Conference on Nanoelectronics, Nanophotonics, Nanomaterials, Nanobioscience &Amp; Nanotechnology (5NANO

View full text Add to dashboard Cite

Dielectric Separated Independent Gates Junctionless Transistor (DSIG-JLT) For Highly Scaled Digital Logic Implementation

Cited by 3 publications

References 29 publications

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

Performance Improvement for Reconfigurable Processor System Design in IoT Health Care Monitoring Applications

Performance Enhancement of Asymmetrical Double Gate Junctionless CMOS Inverter With 3-nm Critical Feature Size Using Charge Sheet

Impact of Channel Thickness on the Performance of JL-DG MOSFET based NAND, NOR, and NOT Logic Gates

Contact Info

Product

Resources

About