Die-to-Wafer Bonding of Thin Dies using a 2-Step Approach; High Accuracy Placement, then Gang Bonding

Abstract

25 um thick dies, mounted on thick carrier die, were placed on a 300mm landing wafer using the High Accuracy Die Bonder SET-FC300. The bonding process was either Cu/Cu or Cu/Sn with respective pitch of 10μm and 40μm. A special test structure was designed on the landing die to electrically determine the alignment accuracy after bonding - both with respect to the X-Y alignment and the rotation. Stacks were then assembled by collective hybrid bonding process. The top die is aligned and placed on the landing wafer coverer by a patterned polymer acting as a temporary alignment holder, and then the populated wafer is moved to a wafer bonder where all the dies are collectively bonded. Electrical measurements on the alignment structures indicate that maximum misalignment of the TSV to the landing pad is in the range of 1.5–1.75 um and the maximum rotation of the die is 0.03 degrees.

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

“…On one hand, the analysis in Ref. [63] shows that either chip-to-wafer or waferto-wafer stacking might be more cost-effective, depending on the chip area and production volume; on the other hand, for the wafer-to-wafer approach, low yield could greatly increase the cost due to the loss of good dies, especially for large chips [64].…”