Die-Package-PCB Signal Integrity Performance Debug of a High-Speed (25Gbps) Retimer: Simulation to Measurement Correlation

Tang, Tony; Wray, Bridger; Murugan, Rajen

doi:10.1109/emcsi38923.2020.9191568

Cited by 3 publications

(6 citation statements)

References 3 publications

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“…Re-spin process takes several methodologies including schematic designing, PCB lay-out and design, debugging [20], and correlation of data [21]. In schematic designing, factors such as restriction of hazardous substance (RoHS) compliance, the tolerances of components, and phase out or component retirement are considered.…”

Section: Methods 21 Re-spinningmentioning

confidence: 99%

Single board re-spin for testing bridge transducer products

Rama

Tocama

Ortiz

et al. 2022

IJEECS

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Integrated circuit (IC) testing involves equipment and product interface board setup. Complex interfaces and obsolete components are some of the factors affecting the board functionality which results in manufacturing downtime. The legacy boards must be simplified so that it needs advanced tools for the lay-out and designing of test boards. This study proposes a solution for board functionality issues by re-spinning the legacy two-board interface into a single board interface. It converts the standard use of boards and standard contacting to single board interface (SBI) and plunge-to-board (PTB) contacting. As a result, the setup time is improved, minimizing board and system repair due to mismatch and contact issues. The board endorsement for contact issues were trimmed from 82 to 46 counts. Other board related issues are decreased by 60% based on the analysis of the correlation in the processes. Additionally, mismatches, which are system issues, are lessened which promotes fixtures maintainability.

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Section: Methods 21 Re-spinningmentioning

confidence: 99%

Single board re-spin for testing bridge transducer products

Rama

Tocama

Ortiz

et al. 2022

IJEECS

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“…It shows that the retimer contains the CDR function and can effectively filter the received signal jitter, but the complex high-speed retimer will lead to a poor quality recovery signal due to timing constraints, and it is easy to timeout and increase the line latency. Figure 1 shows a retimer circuit design based on a typical component of the retimer implementation [7]. As shown in Figure 1, the process of CDR recovery data sent out again goes through parallel-in serial-out (PISO) conversion, decoding and descrambling, and first in first out (FIFO) timing adjustment, which are time consuming.…”

Section: Retimer Circuit Latency and Jitter Performance Analysismentioning

confidence: 99%

“…D n [5] D n [4] D n [3] D n [2] D n [1] D n [0] D n [6] D n [7] d n [2] d n [1] d n [0] The waveform filter is used to logically combine the data judgment decoding result dn[2:0] of the current moment with the data judgment decoding results dn−1[2:0] and dn-2[2:0] of the previous two moments to obtain the signal mode[2:0] of the 3-bit screening mode. The waveform filter consists of two isomorphic data comparators and a waveform selector.…”

Section: Brpdmentioning

confidence: 99%

“…In the literature [6], a retiming driver based on clock and data recovery (CDR) + vertical cavity surface emitting laser (VCSEL) architecture was designed for 50 Gbps PAM4 (pulse-amplitude-modulation-4) signal. To address the challenges posed by signal characteristics, skinning effects, dielectric losses, and inter-symbol crosstalk, the retimer of the repeater type was chosen as the signal conditioning technique in the literature [7]. The retimer consists of a receiver and a driver that uses the clock recovered from the data stream by the CDR or a reference clock to achieve synchronous driving of the data.…”

Section: Introductionmentioning

confidence: 99%

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A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

et al. 2023

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As the PCIe 6.0 specification places higher requirements on signal integrity and transmission latency, it becomes especially important to improve signal transmission performance at the physical layer of the transceiver interface. Retimer circuits are a key component of high-speed serial interfaces, and their delay and jitter size directly affect the overall performance of PCIe. For the typical retimer circuit with large-latency and low-jitter performance, this paper proposes a low-latency and low-jitter Retimer circuit based on CDR + PLL architecture for PCIe 6.0, using a jitter-canceling filter circuit to eliminate the frequency difference between the retiming clock and data, reduce the retiming clock jitter, and improve the quality of Retimer output data. The data are sampled using the retiming clock and then output, avoiding the problem of large penetration latency of typical retimer circuits. The circuit is designed using the CMOS 28 nm process. Simulation results show that when 112 Gbps PAM4 data are input to the retimer circuit, the Retimer penetration latency is 27.3 ps, which is 83.5% lower than the typical Retimer structure; the output jitter data are 741 fs, a 31.4% reduction compared to the typical retimer structure.

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“…A debugger software tool helps determine the failure of the test parameter [26]. To compare the old and the new board correlation is used where the data from serial testing of the known good unit device are compared with respect to each parameter to determine the performance and functionality [27]. Once the old and new board is correlated, it is now ready for production.…”

Section: The Flow Processesmentioning

confidence: 99%

Mitigating board endorsement through re-spinning with surface-mounted device under test pad

Malimban

Ortiz

Enojas

2022

IJEECS

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The two-part legacy board device under test (DUT) pad has been very useful for testing of microelectronic packages. However, <span lang="EN-US">this board has been subjected to many repair endorsements due to open connection of DUT pad and cut traces of the board components as recorded. Board re-spin is used to improve the performance of the test boards in microelectronic packages production. It improves the board development to create more functional printed circuit boards for testing and introduces the use of modern tools and software applied to the schematic creation up to the production board debugging. This paper presents a method of creating test boards for the development and manufacturing of microelectronic packages and integrated circuits. The two-part board is converted into a single board interface which eliminates the open DUT connections. A surface-mounted DUT pad is introduced to replace the old hypertact pins which are included in the re-spin board for a more robust performance. The schematic creation and board debugging were done to lessen problems caused by connection faults. In result, producing re-spin boards mitigates board endorsement which in return increases the manufacturing output performance. A faster and convenient setup was achieved when the old two-board setup was </span>eliminated.

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Die-Package-PCB Signal Integrity Performance Debug of a High-Speed (25Gbps) Retimer: Simulation to Measurement Correlation

Cited by 3 publications

References 3 publications

Single board re-spin for testing bridge transducer products

Single board re-spin for testing bridge transducer products

A Low-Latency, Low-Jitter Retimer Circuit for PCIe 6.0

Mitigating board endorsement through re-spinning with surface-mounted device under test pad

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