Die Attach Film Application in Multi Die Stack Package

Song, Shao; Tan, HB; Ong, Pang-Hup

doi:10.1109/eptc.2005.1614517

Cited by 25 publications

(14 citation statements)

References 2 publications

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“…The XRD/3DSM of the UQFN package clearly reveals that the warpage is relatively low at the corners of the Si die and increases gradually approaching the chip centre and also near the central edges of the die. This non-uniformly distributed warpage is thought to be due to process-induced thermal stress as a result of the CTE mismatch between different materials, most probably from the die attach process [7][8][9][10][11]. Smaller stresses are typically generated during later processing stages, for instance, during the molding compound encapsulation process and thermal cycling reliability testing.…”

Section: Iv) Finite Element Analysis (Fea)mentioning

confidence: 99%

“…In general, the die attach process comprises of the attachment of the die onto the lead frame and the curing of the bonding adhesive at an elevated temperature (> 100 o C) [18,21]. Assuming a similar die attach process was used for the UQFN package under test, wherein an epoxy glue was applied to the Si die, and that the thermosetting adhesive crosslinks and hardens during the adhesive curing process, this most likely generates thermal stress upon cooling down to room temperature [7][8][9][10][11], as illustrated in Figs. 5e)-f).…”

Section: Iv) Finite Element Analysis (Fea)mentioning

confidence: 99%

“…results confirms the aforementioned assumption where the underlying copper lead frame expands more rapidly than that of Si die at elevated temperature, and compensates and relaxes the warpage generated initially during the die attach process. Therefore, it is believed that most of the stress appears to develop during curing of the die-attach adhesive, due to the difference in expansion of the Si die and lead frame, as reported by several authors [7][8][9][10][11].…”

Section: σ XX + σ Yy ) = E[(t*∆ω Bragg )/2∆d]mentioning

confidence: 99%

“…die bond pad, die attach adhesive/epoxy glue, moulding compounds and Cu-filled through-silicon-vias (TSVs) [2][3][4][5][6]. Thermal stress and warpage are frequently generated in the packaged chip during the thermal processing steps as a consequence of the CTE mismatch of these materials [7][8][9][10][11]. Other factors such as the bonding of wires to the die itself [3], thinning of the wafer/die below 100 µm and embedding/lamination processes can also lead to stress and induced warpage/material deformation [12][13].…”

Section: Introductionmentioning

confidence: 99%

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Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Wong¹,

Bennett²,

Manessis³

et al. 2014

Microelectronic Engineering

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Reliability issues as a consequence of thermal/mechanical stresses created during packaging processes have been the main obstacle towards the realisation of high volume 3D Integrated Circuit (IC) integration technology for future microelectronics. However, there is no compelling laboratory-based metrology that can non-destructively measure or image stress/strain or warpage inside packaged chips, System-on-Chip (SoC) or System-in-Package (SiP), which is identified as a requirement by the International Technology Roadmap for Semiconductors (ITRS). In the work presented here, a triple-axis Jordan Valley Bede D1 X-ray diffractometer is used to develop a novel lab-based technique called X-ray diffraction 3-dimensional surface modeling The feasibility of this technique is confirmed through the charactersation of die stress inside 2 encapsulated commercially available ultra-thin Quad Flat Non-lead (QFN) packages, as well as die stress in embedded QFN packages at various stages of the chip manufacturing process.

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Section: Iv) Finite Element Analysis (Fea)mentioning

confidence: 99%

Section: Iv) Finite Element Analysis (Fea)mentioning

confidence: 99%

Section: σ XX + σ Yy ) = E[(t*∆ω Bragg )/2∆d]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Wong¹,

Bennett²,

Manessis³

et al. 2014

Microelectronic Engineering

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show abstract

“…By comparison to epoxy, the DAF requires some bonding delay and temperature to allow the DAF to melt, solidifies and stick to the leadframe or die. Previous study has indicated that most of the die stress is developed during die attach and curing process [2,3,[5][6][7] . When the die stress in the assembly processes is compared, it is found that DAF showed 42% lower stress than epoxy [7] .…”

Section: Introductionmentioning

confidence: 99%

Effect of Manufacturing Stresses to Die Attach Film Performance In Quad Flatpack No-Lead Stacked Die Packages

Aviral¹

2009

American Journal of Engineering and Applied Sciences

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Problem statement: Repeated heat cure during assembly processes affected the Die Attach Film (DAF) material properties and the effectiveness touched area that leads to weak die bonding and delamination. Suitable die attached condition and DAF material selection had been evaluated to achieve required reliability performance in the manufacturing of the 3D Quad Flat No-Lead (QFN) stacked die package. Approach: During this study, special attention was given to the development of the residual stresses due to mismatch in the coefficients of thermal expansion of different DAF materials. Both experimental and finite element method were employed to gain a better understanding in a stress development induced between two different type of DAF, different die attach temperature and during the manufacturing process. Differential scanning calorimetry (DSC) was used to measure the changes of heat flow characteristics for both types of DAF. The die bond strength results measured using shear testing machine were compared with the finite element method prediction. Results: Although both DAF samples achieved good reliability performance and passed the Moisture Sensitivity Level 3 test (MSL3) at reflow 260°C without any sign of delamination, numerical simulation had demonstrated that the stress development were increased exponentially as the die attach temperature increased. It showed that different DAF gave different values of stresses but presented the same trend which the lowest die attached temperature (100°C in comparison with 125°C and 150°C) gave more stress to the die and possibility that the die will have weak adhesion to the substrate was high. Conclusions/Recommendations: Therefore for this case, stress can be relieved by having higher die attached temperature with an adequate bonding force and time, however die attached temperature for both DAF must be used above the glass transition temperature (128°C for DAF A and 165°C for DAF B) and being controlled not to exceed the crystallization temperature (203°C for DAF A and 204°C for DAF B) of both DAF.

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Failure Analysis – What?

Bazu

Băjenescu

2011

Failure Analysis

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Die Attach Film Application in Multi Die Stack Package

Cited by 25 publications

References 2 publications

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Non-destructive laboratory-based X-ray diffraction mapping of warpage in Si die embedded in IC packages

Effect of Manufacturing Stresses to Die Attach Film Performance In Quad Flatpack No-Lead Stacked Die Packages

Failure Analysis – What?

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