DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

Maru, A.; Shindou, H.; Ebihara, T.; Makihara, A.; Hirao, Toshio; Kuboyama, S.

doi:10.1109/tns.2010.2086481

Cited by 15 publications

(6 citation statements)

References 12 publications

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“…In this paper, Cadence's Spectre simulation software is used to simulate the DICE unit of the separated-bit-line and the peripheral circuit strengthened by dual-mode redundancy.In semiconductor integrated circuits, a large number of charges will be generated by single-particle bombardment, and pulse current will be formed under the action of electric field. Usually, the method of injecting a certain width of pulse current into sensitive nodes is used to simulate single-particle bombardment [4].…”

Section: Design and Implementationmentioning

confidence: 99%

Single Event Upset Hardened Design of SRAM Circuits

He¹,

Huang²,

Wu³

2019

dtcse

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As a very important component of integrated circuits, static memory is particularly sensitive to single event effects in outer space.In order to ensure the normal function of integrated circuits, radiation hardening of static memory is particularly important.The traditional reinforcement technology based on DICE structure has weak ability to resist dynamic SEU. A separated-bit-line structure is proposed to handle the DICE cells upset during reading and writing, and a double module redundancy method is presented to resolve the upset in the peripheral circuits. The results show these methods are effective to mitigate SEU from DICE cell based SRAMs.

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Section: Design and Implementationmentioning

confidence: 99%

Single Event Upset Hardened Design of SRAM Circuits

He¹,

Huang²,

Wu³

2019

dtcse

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“…Possible solutions are the extension of registers with ECC [3] or the use of Dual Interlocked CEll flip flops (DICE) [4]. These protection schemes induce higher chip costs, thus it is not practical to protect all registers.…”

Section: A Fault Injection Into Registersmentioning

confidence: 99%

“…In hardware, error correcting codes (ECC) and additional registers with a delayed clock have been shown to reliably protect a microprocessor [3]. On a lower level, DICE-based flip-flops with an SET pulse discriminator are also able to tolerate SEUs and SETs [4]. Software approaches like SWIFT detect transient faults by extending the original program with new validating instructions on the assembler level [5].…”

Section: Introductionmentioning

confidence: 99%

Identification of critical variables using an FPGA-based fault injection framework

Riefert

Müller

Sauer

et al. 2013

2013 IEEE 31st VLSI Test Symposium (VTS)

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Abstract-The shrinking nanometer technologies of modern microprocessors and the aggressive supply voltage down-scaling drastically increase the risk of soft errors. In order to cope with this risk efficiently, selective hardware and software protection schemes are applied. In this paper, we propose an FPGA-based fault injection framework which is able to identify the most critical registers of an entire microprocessor. Furthermore, our framework identifies critical variables in the source code of an arbitrary application running in its native environment. We verify the feasibility and relevance of our approach by implementing a lightweight and efficient error correction mechanism protecting only the most critical parts of the system. Experimental results with state estimation applications demonstrate a significantly reduced number of critical calculation errors caused by faults injected into the processor.

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“…For example, F-DICE [6], Delta DICE [7] and DONUT latches [8], [9] have multiple-nodeupset (MNU) tolerant capability while the original DICE is capable of tolerating only SNUs. The DF-DICE [10] and the FF of [11] is capable of tolerating single-event-transients (SETs) as well as SEUs by using delay elements.…”

Section: Introductionmentioning

confidence: 99%

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge

Namba

2020

IEICE Trans. Inf. & Syst.

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This letter reveals that an edge-triggered master-slave flipflop (FF) using well-known soft error tolerant DICE (dual interlocked storage cell) is vulnerable to soft errors occurring around clock edge. This letter presents a design of a soft error tolerant FF based on the master-slave FF using DICE. The proposed design modifies the connection between the master and slave latches to make the FF not vulnerable to these errors. The hardware overhead is almost the same as that for the original edge-triggered FF using the DICE.

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DICE-Based Flip-Flop With SET Pulse Discriminator on a 90 nm Bulk CMOS Process

Cited by 15 publications

References 12 publications

Single Event Upset Hardened Design of SRAM Circuits

Single Event Upset Hardened Design of SRAM Circuits

Identification of critical variables using an FPGA-based fault injection framework

Master-Slave FF Using DICE Capable of Tolerating Soft Errors Occurring Around Clock Edge

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