DIBL in short-channel NMOS devices at 77 K

Deen, M. Jamal; Yan, Z.X.

doi:10.1109/16.127482

Cited by 51 publications

(19 citation statements)

References 10 publications

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“…However, as demonstrated previously, low-temperature DIBL occurs already for long transistors &=l0 pm) in the case of a 3 pm CMOS technology on high-resistivity (HR) substrates [27]. In general, it is found that the reduction of the threshold voltage, occumng for larger lateral fields (larger VDS) diminishes upon cooling to 77 K, both for n-MOSFETs [28], [29] and p-MOSFETs [30], [31].…”

Section: Charge Threshold Voltage Extractionmentioning

confidence: 97%

Parameter Extraction of MOSFETs Operated at Low Temperature

Simoen

Claeys

Martino³

1996

J. Phys. IV France

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Abstract. In this paper, an overview is given of the methods for practical parameter extraction for MOSFETs operated at cryogenic temperatures. The methods considered are based on the input characteristics of the device, from which the charge threshold voltage, the subthreshold slope, the effective mobility, the series resistance and the effective gate length is derived. Whenever possible, the physical basis of the mostly semi-empirical methods will be outlined. Finally, pitfalls and problems, related to low temperature MOSFET characterisation, like transient and freeze-out effects, self-heating, etc, are briefly discussed.

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Section: Charge Threshold Voltage Extractionmentioning

confidence: 97%

Parameter Extraction of MOSFETs Operated at Low Temperature

Simoen

Claeys

Martino³

1996

J. Phys. IV France

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“…The most widely used such abstraction is the threshold voltage Vi . We therefore proceed by choosing a nominal threshold voltage of the form (9.13) The actual threshold voltage will be lower than the nominal one by the amount of drain-induced barrier lowering (DIEL) (24)(25)(26)(27). In this study, I use the expression given by Fjeldly and Shur (28]:…”

Section: Threshold Scalingmentioning

confidence: 99%

Scaling of MOS technology to submicrometer feature sizes

Mead

1994

Analog Integr Circ Sig Process

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Industries based on MOS technology now play a prominent role in t he developed and the developing world. j\fore importantly, MOS techn ology drives a large proportion of innovation in many technologies . It is likely th at the course of technological development depends more on the capability of MOS technology than on any other technical factor . T herefore, it is worthwhile investigating the na.ture and limits of future improvements to MOS fabrication. The key to improved MOS technology is r eduction in feature size. Reduction in feature size, and the attendant changes in device behaviour, will shape the nature of effective uses of the technology at t he system level. This paper reviews recent, and historical, data on feature scaling and device behavior, and attempts to predict the limits to this scaling. We conclude wi th som e remarks on the system-level implications of fea.ture size as the minimum size approach es physical limits. IntroductionIt is always difficult . to nredict the future; few attemp ts to do so have met with resounding su ccess. One remarkable example of successful prediction is the exponential increase in complexity of integrated circuits, first noted by Gordon E . !vioor e. As we contemplate the ongoing evolution of this great technology, many questions arise: Can the trend continue? Will single-chip systems attain levels of complexity that render present system archit ectures unworkable [lj? vVill digital t.echniques completely replace analog methods [2]"7 The answers to these questions depend critically on the properties of the individual transistor s that provide the essential active functions, without which no interesting system beh avior is possible. Integrated-circuit density is increased by a reduction in the size of elementary feat.ures of the underlying structures; therefore, any discussion of the capabilities of future technologies must rely on an understanding of how the properties of transistors evolve as the transistor s' dimensions are made smaller.Elsewhere [3], we described the factors that limit how small an MOS transistor *Reproduced from Journal of VLSI Signal P rocessing, 8 , 9-25 (1994) Kluwer Academic Publishers, Boston. ~fanufacture d in The Netherlands.

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“…Aiming to observe this effect, the drain induced barrier lowering (DIBL) [10] curve is plotted in figure 4.…”

Section: Results and Analysismentioning

confidence: 99%

The effect of X-Ray radiation on DIBL for standard and strained triple-gate SOI MuGFETs

Bordallo

Teixeira

Silveira

et al. 2014

2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)

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This study presents an experimental analysis of the Xray radiation effect on the drain induced barrier lowering (DIBL) of strained and unstrained, p and n type triple gate SOI MuGFETs. In both types of devices, the narrow fin transistors are more immune to radiation because of the better coupling among the gates. It is shown that total dose damage in nMuGFETs always leads to a performance degradation, based on the subthreshold region characteristics studied. For pMuGFETs, radiation is not always harmful, because it reduces the leakage current, improving the subthreshold swing of the drain current. However, for devices that are less sensitive to this leakage current, the radiation-induced interface traps become the predominant damage mechanism.

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DIBL in short-channel NMOS devices at 77 K

Cited by 51 publications

References 10 publications

Parameter Extraction of MOSFETs Operated at Low Temperature

Parameter Extraction of MOSFETs Operated at Low Temperature

Scaling of MOS technology to submicrometer feature sizes

The effect of X-Ray radiation on DIBL for standard and strained triple-gate SOI MuGFETs

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