DianNao

Chen, Tianshi; Du, Zidong; Sun, Ninghui; Wang, Jia; Wu, Chunlin; Temam, Olivier

doi:10.1145/2541940.2541967

Cited by 915 publications

(63 citation statements)

References 28 publications

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“…Our baseline Single-CLP design is based on [32]. Similar designs are used in [4,5]. Other recent works propose different CNN acceleration hardware.…”

Section: Related Workmentioning

confidence: 99%

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Shen

Ferdman

Milder

2017

Proceedings of the 44th Annual International Symposium on Computer Architecture

201

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Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based accelerators have been proposed to improve the performance and efficiency of CNNs. Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection of layers is computed. However, this approach leads to inefficient designs because the same processor structure is used to compute CNN layers of radically varying dimensions.We present a new CNN accelerator paradigm and an accompanying automated design methodology that partitions the available FPGA resources into multiple processors, each of which is tailored for a different subset of the CNN convolutional layers. Using the same FPGA resources as a single large processor, multiple smaller specialized processors increase computational efficiency and lead to a higher overall throughput. Our design methodology achieves 3.8x higher throughput than the state-of-the-art approach on evaluating the popular AlexNet CNN on a Xilinx Virtex-7 FPGA. For the more recent SqueezeNet and GoogLeNet, the speedups are 2.2x and 2.0x. ] for (r =0; r

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“…Our baseline Single-CLP design is based on [32]. Similar designs are used in [4,5]. Other recent works propose different CNN acceleration hardware.…”

Section: Related Workmentioning

confidence: 99%

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Shen

Ferdman

Milder

2017

Proceedings of the 44th Annual International Symposium on Computer Architecture

201

View full text Add to dashboard Cite

show abstract

“…The computationally intensive model of the neural network is mainly embodied in a large number of multiplication operations. Although a variety of neural network accelerator solutions have been proposed [8][9][10][11][12], most of the work remain in the solution to the problem of access and data path design, and do not really go deep into the underlying multiplication unit.…”

Section: Introductionmentioning

confidence: 99%

EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier

Wang

Xia

Liu

et al. 2018

IEICE Electron. Express

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Abstract:This paper proposes an energy-efficient reconfigurable architecture for deep neural networks (EERA-DNN) with hybrid bitwidth and logarithmic multiplier. To speed up the computing and achieve high energy efficiency, we first propose an efficient network compression method with hybrid bit-width weights scheme, that saves the memory storage of network LeNet, AlexNet and EESEN by 7x-8x with negligible accuracy loss. Then, we propose an approximate unfolded logarithmic multiplier to process the multiplication operations efficiently. Comparing with state-of-the-art architectures EIE and Thinker, this work achieves over 1.8x and 2.7x better in energy efficiency respectively.

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“…[1,2,3,4] Due to the specific computation pattern of CNN, general purpose processors hardly meet the implementation requirement, which encourages the proposal of various hardware implementations based on FPGA, GPU and ASIC [5,6,7]. CNN contains numerous 2D convolutions, which are responsible for more than 90% of the whole computation [8].…”

Section: Introductionmentioning

confidence: 99%

An efficient implementation of 2D convolution in CNN

Jing

Sha

2017

IEICE Electron. Express

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Convolutional neural network (CNN), a well-known machine learning algorithm, has been widely used in the field of computer vision for its amazing performance in image classification. With the rapid growth of applications based on CNN, various acceleration schemes have been proposed on FPGA, GPU and ASIC. In the implementation of these specific hardware accelerations, the most challenging part is the implementation of 2D convolution. To obtain a more efficient design of 2D convolution in CNN, this paper proposes a novel technique, singular value decomposition approximation (SVDA) to reduce the usage of resources. Experimental results show that the proposed SVDA hardware implementation can achieve a reduction in resources in the range of 14.46% to 37.8%, while the loss of classification accuracy is less than 1%.

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DianNao

Cited by 915 publications

References 28 publications

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

Maximizing CNN Accelerator Efficiency Through Resource Partitioning

EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier

An efficient implementation of 2D convolution in CNN

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