Diamond matrix powers kernels

Vatai, Emil; Singhal, Utsav; Suda, Reiji

doi:10.1145/3368474.3368494

Cited by 2 publications

(3 citation statements)

References 7 publications

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“…Future work in this direction includes integrating RACE MPK into communication-avoiding s-step Krylov solvers and polynomial preconditioners from the Trilinos [51] framework. For multi-node MPK computations, our level-based cache blocking scheme can be integrated with existing ideas (e.g, [11], [24]) to enable a highly efficient distributed MPK scheme with low inter-node communication overhead. Another interesting research direction that we are currently pursuing is the development of a GPU implementation for the cacheblocked MPK method.…”

Section: Discussionmentioning

confidence: 99%

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Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

Alappat¹,

Hager²,

Schenk

et al. 2023

IEEE Trans. Parallel Distrib. Syst.

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The multiplication of a sparse matrix with a dense vector (SpMV) is a key component in many numerical schemes and its performance is known to be severely limited by main memory access. Several numerical schemes require the multiplication of a sparse matrix polynomial with a dense vector which is typically implemented as a sequence of SpMVs. This results in low performance and ignores the potential to increase the arithmetic intensity by reusing the matrix data from cache. In this work we use the recursive algebraic coloring engine (RACE) to enable blocking of sparse matrix data across the polynomial computations. In the graph representing the sparse matrix we form levels using a breadth-first search. Locality relations of these levels are then used to improve spatial and temporal locality when accessing the matrix data and to implement an efficient multithreaded parallelization. Our approach is independent of the matrix structure and avoids shortcomings of existing "blocking" strategies in terms of hardware efficiency and parallelization overhead. We quantify the quality of our implementation using performance modelling and demonstrate speedups of up to 3× and 5× compared to an optimal SpMV-based baseline on a single multicore chip of recent Intel and AMD architectures. Various numerical schemes like s-step Krylov solvers, polynomial preconditioners and power clustering algorithms will benefit from our development.

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Section: Discussionmentioning

confidence: 99%

“…Most of the other works [11], [21], [22], [23] on MPK schemes focused on reducing the MPI communication overhead. A recent work [24] in this direction presents a theoretical study on the benefit of diamond tiling for reducing communication.…”

mentioning

confidence: 99%

Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

Alappat¹,

Hager²,

Schenk

et al. 2023

IEEE Trans. Parallel Distrib. Syst.

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show abstract

“…Most of the other works [11], [18], [19] on MPK schemes focused on reducing the MPI communication overhead. A recent work [20] in this direction presents a theoretical study on the benefit of diamond tiling for reducing communication.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Level-based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

Alappat,

Hager,

Schenk

et al. 2022

Preprint

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The multiplication of a sparse matrix with a dense vector (SpMV) is a key component in many numerical schemes and its performance is known to be severely limited by main memory access. Several numerical schemes require the multiplication of a sparse matrix polynomial with a dense vector which is typically implemented as a sequence of SpMVs. This results in low performance and ignores the potential to increase the arithmetic intensity by reusing the matrix data from cache. In this work we use the recursive algebraic coloring engine (RACE) to enable blocking of sparse matrix data across the polynomial computations. In the graph representing the sparse matrix we form levels using a breadth-first search. Locality relations of these levels are then used to improve spatial and temporal locality when accessing the matrix data and to implement an efficient multithreaded parallelization. Our approach is independent of the matrix structure and avoids shortcomings of existing "blocking" strategies in terms of hardware efficiency and parallelization overhead. We quantify the quality of our implementation using performance modelling and demonstrate speedups of up to 3× and 5× compared to an optimal SpMV-based baseline on a single multicore chip of recent Intel and AMD architectures. As a potential application, we demonstrate the benefit of our implementation for a Chebyshev time propagation scheme, representing the class of polynomial approximations to exponential integrators. Further numerical schemes which may benefit from our developments include s-step Krylov solvers and power clustering algorithms.

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Diamond matrix powers kernels

Cited by 2 publications

References 7 publications

Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

Level-Based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

Level-based Blocking for Sparse Matrices: Sparse Matrix-Power-Vector Multiplication

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