2008
DOI: 10.1109/led.2008.923710
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Diamond-Like Carbon (DLC) Liner: A New Stressor for P-Channel Multiple-Gate Field-Effect Transistors

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Cited by 13 publications
(8 citation statements)
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“…1(b)], however, reduced the stress contribution from the DLC liner in this letter as compared to [9] where the higher I on enhancement is also due to higher DLC stress, shorter L G , and, possibly, compliance effect of silicon-oninsulator (SOI) substrates. Reference [10] demonstrated 34% I on enhancement for SOI FinFET with raised Si S/D (15 nm) and L G of 70 nm, but the higher enhancement is also due to higher DLC stress and shorter L G . Ge condensation of SiGe S/D [12] or increasing stress coupling of SiGe S/D using a wrap-around structure [13] contributed to ∼28% and ∼26% I on enhancements, respectively, which are higher than that due to the DLC reported here.…”
Section: Resultsmentioning
confidence: 99%
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“…1(b)], however, reduced the stress contribution from the DLC liner in this letter as compared to [9] where the higher I on enhancement is also due to higher DLC stress, shorter L G , and, possibly, compliance effect of silicon-oninsulator (SOI) substrates. Reference [10] demonstrated 34% I on enhancement for SOI FinFET with raised Si S/D (15 nm) and L G of 70 nm, but the higher enhancement is also due to higher DLC stress and shorter L G . Ge condensation of SiGe S/D [12] or increasing stress coupling of SiGe S/D using a wrap-around structure [13] contributed to ∼28% and ∼26% I on enhancements, respectively, which are higher than that due to the DLC reported here.…”
Section: Resultsmentioning
confidence: 99%
“…Ge condensation of SiGe S/D [12] or increasing stress coupling of SiGe S/D using a wrap-around structure [13] contributed to ∼28% and ∼26% I on enhancements, respectively, which are higher than that due to the DLC reported here. When comparing I on enhancement due to SiGe S/D [12] or DLC in planar and FinFET devices [10] at a given I off , the following additional factors should be considered: L G , SCE, series resistance, S/D elevation, Ge composition, channel surface orientation, and device topology affecting stress coupling.…”
Section: Resultsmentioning
confidence: 99%
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“…In FinFETs, significant I Dsat enhancement can also be achieved using the SiN liner stressor [8]- [12]. In p-channel FinFETs (p-FinFETs), diamond-like carbon (DLC) liner stressor has been demonstrated for strain engineering [13], [16]. DLC has an intrinsic compressive stress of up to 10 GPa significantly greater than that of SiN and allows a higher channel stress to be induced for a given liner thickness.…”
Section: Introductionmentioning
confidence: 99%
“…INTRODUCTION With scaling of the silicon metal-oxide-semiconductor field-effect transistor (MOSFET) into sub-20 nm technology nodes, the conventional planar device structure would be replaced by the multi-gate or fin field-effect transistor (FinFET) device structure, which has excellent control of short-channel effects (SCEs). [1][2][3][4][5][6][7][8][9][10][11] To boost the switching speed or drive current of FinFETs, carrier mobilities may be enhanced by channel strain engineering. [4][5][6][7][8][9][10][11][12][13][14][15] Recently, a new liner stressor comprising Ge 2 Sb 2 Te 5 (GST) was reported for inducing strain in p-channel FinFETs, significantly increasing the hole mobility and drive current.…”
mentioning
confidence: 99%