Diagnostic data detection of faults in RAM using different march algorithms with BIST scheme

Koshy, Twinkle; Arun, C.

doi:10.1109/icett.2016.7873754

Cited by 10 publications

(9 citation statements)

References 12 publications

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“…This was achieved by dividing the test operations into two subgroups which are executed in parallel: M1: ⇑(w0); ⇑(r0, w1); ⇑(r1); ⇓(w0); ⇓(r0, w1); ⇓(r1) M2: ⇑(w1); ⇑(r1, w0); ⇑(r0); ⇓(w1); ⇓(r1, w0); ⇓(r0) By observing the proposed algorithm, it can be seen that M2 is exactly the complement of M1, and thus, only one test bit generator is adequate for both subgroups, where an inverter is added to invert the test bit for M2. Meanwhile, research in [10] proposes the modification in the memory BIST design to fusion three different algorithms (MATS, March X, and March C) in one design. The proposed technique was proven inefficient in improving the fault detection of the memory BIST, as it only allows the system to select one test algorithm to be used (among three options available) when the circuit is operating, by utilizing a multiplexer.…”

Section: Previous Work On Improving the Memory Testing Algorithmsmentioning

confidence: 99%

“…Therefore, the quality of the memories is the main factor in having a good manufacturing yield [3]- [9]. Testing an embedded memory like a DRAM and SRAM can be very challenging, due to its extreme density [10]. Furthermore, most IC chips are manufactured using very deep submicron (VDSM), more defects are occurring during the chip fabrication process resulting in complex chip testing [9], [11]- [13].…”

Section: Introductionmentioning

confidence: 99%

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A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

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Section: Previous Work On Improving the Memory Testing Algorithmsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A review paper on memory fault models and test algorithms

Jidin

Hussin

Fook³

et al. 2021

Bulletin EEI

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show abstract

“…a single cell and two cells fault models. For single-cell fault model, it consists of Stuck-At Fault (SAF), Transition Fault (TF), and Data Retention Fault (DRF) [10][11][12].…”

Section: Memory Fault Detection Algorithmsmentioning

confidence: 99%

“…There are various memory test algorithms were introduced to test the memory devices [6,[10][11][12]. The conventional test algorithms are zero-one and checkboard scan tests.…”

Section: Introductionmentioning

confidence: 99%

VHDL Modelling of Low-CostMemory Fault Detection Tester

Chun

Leong

Yoong

et al. 2020

JETAP

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Memory modules are widely used in varies kind of electronics system design. The capacity of the memory modules has increased rapidly since the past few years in order to satisfy the high demand from the end-users. The memory modules’ manufacturers demand more units of automatic test equipment (ATE)to increase the production rate. However, the existing ATE used in the industry to carry out the memory testing is too costly(at least a million dollars per ATE tester). The low-cost memory testers are urgently needed to increase the production rate of the memory module. This has in spired us to design a low-cost memory tester. A low-cost memory fault detection tester with all the major fault detection algorithms that used in industry is modelled using Very High Speed Integrated Circuit Hardware Description Language (VHDL) in this paper to support the need of the low-cost ATE memory tester. The fault detection algorithms modelled are MATS+ (Modified Algorithm Test Sequence), MATS++, March C, March C-, March X ,March Y, zero-one and checkerboard scan tests. PERL program is used to analyse the simulation results and a log file will be generated at the end of the memory test. Extensive simulation and experimental test results show that the memory tester modelled covers all the memory test algorithms used in the industry. The low-cost memory fault detection tester designed provides the 100% fault detection coverage for all memory defects.

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“…To ensure the characteristics of modern memory of computer systems that meet the requirements of new technological advances, the necessity and importance of testing memory devices have increased sufficiently [1,2]. The main task of memory testing is to detect faulty states described by various models of their failures [3][4][5]. Among the large variety of memory faults, coupling faults, CFs, involve two memory cells, a i and a j .…”

Section: Introductionmentioning

confidence: 99%

Linked Coupling Faults Detection by Multirun March Tests

Mrozek,

Yarmolik

2024

Applied Sciences

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This paper addresses the problem of describing the complex linked coupling faults of memory devices and formulating the necessary and sufficient conditions for their detection. The main contribution of the proposed approach is based on using a new formal model of such faults, the critical element of which is the introduction of roles and scenarios performed by the cells involved in the fault. Three roles are defined such that the cells of the complex linked coupling faults perform, namely, the roles of the aggressor (A), the victim (V), and both (B), performed by two cells simultaneously in relation to each other. The memory march test and applied address sequence and background determine the scenario for implementing the roles of memory faulty cells. The necessary and sufficient conditions for detecting linked coupling faults are given based on a new formal model. Formally, the undetectable linked coupling faults are defined, and the conditions for their detection are formulated using multirun memory march tests. The experimental investigation confirmed the validity of the proposed formulated statements. Based on the example of a linked coupling fault, this study demonstrates the fulfillment of the necessary and sufficient conditions for its detection using a single march test. As demonstrated in this article, employing the approach proposed by the authors, a two-pass march C test, for instance, enables the attainment of 55.42% fault coverage for linked coupling faults, inclusive of undetectable faults identified by the single-pass march test.

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Diagnostic data detection of faults in RAM using different march algorithms with BIST scheme

Cited by 10 publications

References 12 publications

A review paper on memory fault models and test algorithms

A review paper on memory fault models and test algorithms

VHDL Modelling of Low-CostMemory Fault Detection Tester

Linked Coupling Faults Detection by Multirun March Tests

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