DFT Expert: designing testable VLSI circuits

Bhawmik, Sudipta; Palchaudhuri, P.

doi:10.1109/54.43075

Cited by 16 publications

(10 citation statements)

References 13 publications

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“…Note that there is no interstep conflict in this combined schedule. Hence, the minimum value of D is in this case, as contrasted to the value 4 obtained by the existing methods [2,4]. The reason for starting the combination process from the CLB port side is based on the fact that the No-Op steps required for equalizing the paths are pushed towards the pattern generator side, instead of the port side.…”

Section: {Ill}mentioning

confidence: 94%

“…The existing algorithms for test plan generation [2,4] attempt to combine the I-paths, starting from the test pattern generator side (for the input I-paths) and from the port side (for the output I-paths). But this approach may lead to the serious limitation of precluding feasible input I-path combinations even when they exist.…”

Section: Approaching From the Port Sidementioning

confidence: 99%

“…The next marker is placed at (2,4). Since both the D-move and V-move are inhibited at (2,4), an H-move is made to place the next marker at (2,3). The last marker is placed at (1,2) by a diagonal move.…”

Section: I-path Combinationmentioning

confidence: 99%

“…Abadir and Breuer [3] have also considered the problem of pipelining the test vectors through a test plan, and have suggested a lower bound on D. An algorithm for minimizing D by inserting No-ops in the combined test plan has also been presented by them. Bhawmik [4] has formulated these tasks as a consistent labeling problem [5], and has solved it using a backtracking algorithm. However, in these approaches, the problems of I-path combination and D-minimization have been treated separately.…”

Section: Introductionmentioning

confidence: 99%

“…In this paper, we first show that the process of combination of I-paths can affect the lower bound on D. Accordingly, we propose an approach to I-path combination which refrains from increasing the lower bound on D, as far as possible. The earlier algorithms [2,4] carry out the task of I-path combination in the direction of test pattern propagation. However, as shown in the next section, this approach may sometimes inhibit obtaining a feasible combination even if it exists.…”

Section: Introductionmentioning

confidence: 99%

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A Modified Approach to Test Plan Generation for Combinational Logic Blocks

et al. 1996

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Generation of test plans is a crucial step for testing VLSI circuits. This paper presents a modified approach to test plan generation for the BILBO test methodology. A few limitations of the existing approaches have been identified and methods to address these have been suggested. The proposed approach has been implemented for the general case of n-port combinational logic blocks (CLBs). However, due to limitations of space and for clarity, only 2-port CLBs are considered in this paper. For this case, the problem is modelled as a Step Scheduling Matrix and an algorithm is presented for the solution. The algorithm has been tested on a number of benchmark circuits and the results are compared with those obtained through existing methods. The effectiveness of the proposed approach is clear from the results, as it contributes to the reduction in total testing time as well as generates a larger number of test plans.

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Section: {Ill}mentioning

confidence: 94%

Section: Approaching From the Port Sidementioning

confidence: 99%

Section: I-path Combinationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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