Device-Circuit Co-design of Memristor-based on Niobium Oxide for Large-Scale Crossbar Memory

Abstract

Memristor-based crossbar architecture emerges as a promising candidate for 3-D memory and neuromorphic computing; however, the sneak current through the unselected cells becomes a fundamental roadblock for their development as it results in misreading and high power consumption. In this regard, we investigate Pt/Ti/NbO<sub>2/</sub>Nb<sub>2</sub>O<sub>5−x</sub>/Pt-based self-selective memristor, which combines inherent nonlinearity of NbO<sub>2 </sub>switching layer and non-volatile operation of Nb<sub>2</sub>O<sub>5−x </sub>memory layer in a single device. The results show that Pt/Ti/NbO<sub>2</sub>/Nb<sub>2</sub>O<sub>5−x</sub>/Pt memristor offers the sneak current of 310 nA, selectivity of around 174, and on/off current ratio of 4.79 compared to the sneak current of around 70 µA, selectivity of about 4.02, and on/off current ratio of around 1.55 for Pt/Ti/Nb<sub>2</sub>O<sub>5−x</sub>/Pt-based memristor. Our self-selective memristor minimizes the sneak current, but a small on/off current ratio limits their readout margin and power efficiency for crossbar array size greater than 212. Further, we demonstrate that breaking down a large-scale crossbar array into smaller subarrays and separating them by transistor switches is a more efficient way of eliminating the sneak current. The memristor-transistor split crossbar architecture essentially provides the readout margin and power efficiency of subarray for large size crossbar array and allows high-density array integration over 1Transistor-1Memristor architecture.