Development of viscous PR flow technology for 0.26 μm contact pitch on 0.84 μm/sup 2/ SRAM cell [photoresist flow]

For the scaling down of design rule to develop the high density NAND Flash device, the reduced active area forces to form a small bit-line contact with the low contactresistance, as well as the low junction leakage current due to the borderless contact. In this paper, we propose a novel process to make 38nm small size contact with 76nm pitch by using the reversal PR (Photo Resist) and SADP (Self-Align Double patterning) process. The methods to minimize the contact resistance and to suppress the junction leakage current were explained on NAND Flash device with 38nm node technology.

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Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

Hwang

Jaehwang

Park

et al. 2007

2007 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC)

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Development of viscous PR flow technology for 0.26 μm contact pitch on 0.84 μm/sup 2/ SRAM cell [photoresist flow]

Cited by 1 publication

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Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

Smallest Bit-Line Contact of 76nm pitch on NAND Flash Cell by using Reversal PR (Photo Resist) and SADP (Self-Align Double Patterning) Process

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