Development of
            <scp>fault‐tolerant</scp>
            reduced device version with
            <scp>switched‐capacitor</scp>
            based multilevel inverter topologies

Kumar, Dhananjay; Nema, Rajesh Kumar; Gupta, Sushma

doi:10.1002/2050-7038.12893

Cited by 10 publications

(7 citation statements)

References 32 publications

(33 reference statements)

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“…However, voltage and power handling capacity of the reported topologies also varies from authors to authors. Therefore, it would be quite unfair to allocate the same price for the switches with different voltage pressures [21]. However, the article we 6 submitted is critically compared for their international price in USD.…”

Section: Real-time Validation Of Simulation Resultsmentioning

confidence: 99%

Five-Level Cascaded H-Bridge Mli Using New in-Phase Disposition PWM Technique for Harmonics Mitigation, 1-8.

Rathore,

Yadav

2023

International Journal of Power and Energy Systems

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In recent years, multi-phase multilevel inverters (MLIs) with different topologies have been used in various drives due to the potential benefits of multi-phase, over three-phase, in industrial applications.In this paper, performance analysis of five-level cascaded H-bridge multilevel inverter (CHB-MLI) using a new in-phase disposition (IPD) multicarrier pulse width modulation (PWM) technique for harmonic mitigation is presented. In the proposed work, MLI is also implemented with phase disposition (PD), phase opposition disposition (POD), and alternate phase opposition disposition (APOD) PWM techniques. The Matlab/Simulink platform is used to model the proposed topologies. Results obtained from the simulation are compared with the proposed IPD topology. The analysis of resultsshows that the proposed topology mitigates the current and voltage harmonics to 1.7% and 6.15% and increases the system's efficiency with reduced power loss. Finally, the system efficacy is validated by the real-time digital simulator Opal-RT OP4500.

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Section: Real-time Validation Of Simulation Resultsmentioning

confidence: 99%

Five-Level Cascaded H-Bridge Mli Using New in-Phase Disposition PWM Technique for Harmonics Mitigation, 1-8.

Rathore,

Yadav

2023

International Journal of Power and Energy Systems

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“…The topology presented in [26]- [28] can continue to give seven level output voltage in the post fault condition for OCF and SCF. The topologies presented in [21], [22] requires two DC sources and the topologies mentioned in [23]- [28] requires three DC sources. But, most of the drive applications use SDCS MLI.…”

Section: B Literature Reviewmentioning

confidence: 99%

A Seven Level Fault Tolerant Switched Capacitor Boost Inverter With a Single DC Source

Yarlagadda,

Verma,

Tariq

et al. 2023

IEEE Access

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A Fault-Tolerant Multi-Level Inverter (FT-MLI) is essential to ensure power supply continuity for crucial applications. At the same time, the cost and efficiency of MLI is also important for its successful use in the commercial market. The existing seven level FT-MLI topologies demand more than one input DC source, which increases the cost function. This article proposes a single DC source seven level FT-MLI topology with minimum number of switches (IGBT) to reduce the cost function. The proposed FT-MLI topology generates seven level output voltage with 1.5 times voltage boosting. In case of open or short circuit fault on any single or multi switch, the topology continues to operate with five level output voltage using reserved switches. It consists of eight active switches, two diodes, two capacitors, six thermal fuses, and three reserved switches. In comparison to the existing seven level fault tolerant (open circuit and short circuit fault) topologies, the suggested structure requires minimum number of component count. The efficiency and power losses of the proposed structure are analyzed theoretically. The proposed topology has an efficiency of 96 % at an output power of 600 W under healthy condition and 97% at an output power of 272 W under post fault condition. The level shift pulse width modulation approach is used to generate required triggering pulse for the switch during pre-fault and post-fault. The proposed topology is simulated in the MATLAB/Simulink platform and experimentally verified using dSPACE 1104. The response of the output voltage and current during the transition from pre-fault to post-post fault for each switch fault are presented.

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“…A single-phase seven-level FT MLI is proposed in [68], and it is shown in Figure 33. It comprises two DC sources, two capacitors, three bidirectional switches, and six unidirectional switches.…”

Section: Tp36mentioning

confidence: 99%

Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

et al. 2022

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Multilevel inverters (MLIs) are used in a variety of industrial applications in high- and medium-voltage systems. The modularity, high-power output from medium voltages, and low harmonic content are some of the advantages of MLIs. The reliability of MLIs is quite important. The reliability is affected by different kinds of faults occurring in the MLIs. In MLI circuits, switching devices are the most vulnerable components and have a major involvement in all types of faults. As an outcome, it is necessary to take proper corrective action in the event of a fault. This work provides a comprehensive review of different fault tolerant (FT) solutions for MLIs in the event of switch fault. Moreover, various single-phase FT MLI topologies are reviewed, along with their constructional features, merits, and demerits. This work also proposes a comparison approach that integrates novel factors to account for fault tolerance quantitatively. A comparison investigation verifies the effectiveness of the proposed method. The FT operation of an existing five-level FT MLI topology is discussed, simulated, and experimentally verified.

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Development of fault‐tolerant reduced device version with switched‐capacitor based multilevel inverter topologies

Cited by 10 publications

References 32 publications

Five-Level Cascaded H-Bridge Mli Using New in-Phase Disposition PWM Technique for Harmonics Mitigation, 1-8.

Five-Level Cascaded H-Bridge Mli Using New in-Phase Disposition PWM Technique for Harmonics Mitigation, 1-8.

A Seven Level Fault Tolerant Switched Capacitor Boost Inverter With a Single DC Source

Single-Phase Fault Tolerant Multilevel Inverter Topologies—Comprehensive Review and Novel Comparative Factors

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