Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2019) 2020
DOI: 10.22323/1.370.0090
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Development of Readout Electronics for a Digital Tracking Calorimeter

Abstract: On behalf of the Bergen pCT Collaboration Highly segmented digital tracking calorimeters consist of multiple layers of high-granularity pixel detector CMOS sensors and absorption/conversion layers. Two separate prototypes are being developed: (1) an electromagnetic calorimeter for a proposed ALICE upgrade (during Long Shutdown 3) and (2) a hadronic calorimeter for medical proton computed tomography imaging. These prototypes employ the ALPIDE detector chip developed for the ALICE Inner Tracking System. The ALPI… Show more

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Cited by 2 publications
(6 citation statements)
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“…there is a pileup of events in that frame. With minimum-bias triggers, there are no empty frames 6 since only interaction events are triggered on, and minimum-bias triggers have smaller pileup values 7 . Pileup values larger than three are rarely observed for minimum-bias triggers or periodic triggers with 5 µs period.…”
Section: Simulation Resultsmentioning
confidence: 99%
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“…there is a pileup of events in that frame. With minimum-bias triggers, there are no empty frames 6 since only interaction events are triggered on, and minimum-bias triggers have smaller pileup values 7 . Pileup values larger than three are rarely observed for minimum-bias triggers or periodic triggers with 5 µs period.…”
Section: Simulation Resultsmentioning
confidence: 99%
“…As a final remark, the simulation model has also been used to simulate data rates and readout efficiency for the proton-CT project at the University of Bergen (UiB) [7] and the planned Forward Calorimeter (FoCal) in ALICE.…”
Section: Discussionmentioning
confidence: 99%
“…The 5 μs frame time represents a lowest limit which should never be reached in a real case scenario. System C-simulations [46] with these numbers gave a data rate of roughly 1.4 Gbit/s for each layer [47], as shown in Figure 6.…”
Section: Conceptual Designmentioning
confidence: 99%
“…The pRU is based on a Xilinx Kintex Ultrascale FPGA. The FPGA's native I/O primitives provide high enough bandwidth to handle the 108 data links without employing multi-gigabit transceiver pins reducing the need for a larger and more expensive FPGA [47]. Figure 8 shows the functional block diagram of the pRU.…”
Section: Readout Electronicsmentioning
confidence: 99%
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