Development of Parameterized Model of Logic Elements at Clock Tree Synthesis
V.Sh. MELIKYAN,
A.A. GALSTYAN,
S.A. GHUKASYAN
et al.
Abstract:Clock synthesis, routing optimization, placement and logic optimization are the three primary phases of physical design implementation. Since clock network synthesis uses at least 30% of the entire power budget, it is one of the crucial steps. Power consumption for high-performance blocks can reach 50% of the entire power. Not only would a high-quality clock tree will fix timing violations, but it will also minimize power usage and routing resource use. A new neural network based parameterized model is propose… Show more
Set email alert for when this publication receives citations?
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.