Proceedings of the 2005 Particle Accelerator Conference
DOI: 10.1109/pac.2005.1591332
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Development of Measurement and Transverse Feedback System at HLS

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Cited by 3 publications
(3 citation statements)
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“…After that, a consecutive data segment containing 20 position signals for each bunch (e.g., for the first bunch, B1_0, …B1_19) are extracted by using shift registers (I_SHIFT). Then the outputs of the shift registers are split into two paths, of which one is fed to the FIR filter [13][14][15][16] for feedback information calculation in X direction, and the other is used for the calculation in the Y direction. The 20-order filter is used to process the digitized bunch signal and calculate the feedback data with a correct phase shift, meanwhile rejecting the DC component caused by the equilibrium orbit [17].…”
Section: Design Of Fpga-based Signal Process Algorithmmentioning
confidence: 99%
“…After that, a consecutive data segment containing 20 position signals for each bunch (e.g., for the first bunch, B1_0, …B1_19) are extracted by using shift registers (I_SHIFT). Then the outputs of the shift registers are split into two paths, of which one is fed to the FIR filter [13][14][15][16] for feedback information calculation in X direction, and the other is used for the calculation in the Y direction. The 20-order filter is used to process the digitized bunch signal and calculate the feedback data with a correct phase shift, meanwhile rejecting the DC component caused by the equilibrium orbit [17].…”
Section: Design Of Fpga-based Signal Process Algorithmmentioning
confidence: 99%
“…The HLS BxB system consists of two projects: the BxB measurement system [1] [2] and the BxB transverse analogy feedback system[2] [3]. Signal detection have implemented by Beam Position Monitor (BPM), which has four-button type pick-ups mounted in a skew 45 o [4], and feedback devices is using strip lines.…”
Section: Hls Bunch-by-bunch Systemmentioning
confidence: 99%
“…A 12 bit 500 Msps ADC chip AD9434 is employed in this design. The output of the ADC are then fed to a Field Programmable Gate Array (FPGA) to calculate the feedback coefficients based on Finite Impulse Response (FIR) filters in [7][8][9][10]. These coefficients are used as the input of two 14 bit DAC (AD9736 from Analog Device Inc.) working at 500 MHz, which are used for transverse feedback in the vertical and horizontal (i.e.…”
Section: Introductionmentioning
confidence: 99%