Development of fabrication techniques for high-density integrated MIM capacitors in power conversion equipment

Abstract

In portable electronic equipments, miniaturisation, cost, multi-functionalities and reliability are the main factors driving the power electronics industry. In this context, the realisation of all integrated high performance DC-DC micro-converters working at high frequencies (few MHz) is necessary. The passive components such as inductors, transformers and capacitors, are for the moment the bulkiest components and their integration on silicon substrate would constitute a real improvement in term of compactness and reliability of power converters. This paper deals with the fabrication of integrated capacitors realised on silicon using MEMS-type techniques. High capacitance density, low series resistance and inductance are sought. Structures using deep cavities etched in silicon were realised in order to increase the effective area of the capacitor's electrodes while minimising the area on the substrate. The development of micro-fabrication techniques such as Deep Reactive Ion Etching (DRIE) and doped-polysilicon deep trenches filling are presented. Some preliminary measurement on the fabricated capacitors with the developed processes show that high capacitance density (36 nF/mm²) can be obtained.

Design and realization of highly integrated isolated DC/DC micro-converter

“…These high surface density 3D capacitors can be implemented in the metal layers region (on top of the silicon CMOS technology) thanks to a post process [27]. They can also be directly implemented in the silicon itself thanks to a pre process [28]. In this case, possible interactions with the substrate must be taken into account as a function of the electrode potentials at which the capacitor is to be connected.…”

High-Density 3-D Capacitors for Power Systems On-Chip: Evaluation of a Technology Based on Silicon Submicrometer Pore Arrays Formed by Electrochemical Etching

“…If the contact for the bottom electrode is taken on the rear side of the wafer as schematized in Figure 1, the bulk resistivity of the substrate will be an important factor. Solutions include reducing the thickness of the substrate by CMP (Chemical Mechanical Planarization) or creating cavities at the bottom of the structure [31,32]. If the contact for the bottom electrode is to be taken at the front side, the lateral resistance (R a in Figure 1) will be dominant.…”

Conception de transistors MOS haute tension (1 200 volts) pour l'électronique de puissance

“…Toutes les tranchées sont réalisées par gravure DRIE. La profondeur de la tranchée de terminaison sera plus importante que celle des tranchées fines [73], mais ceci n'est pas néfaste à la tenue en tension de la terminaison. Puis nous faisons croître un oxyde de contrôle et nous déposons du polysilicium saturé en bore ( Figure IV.3 (c)).…”