Development of chip-first and die-up fan-out wafer level packaging

5-in-1 Fan-Out Wafer-Level Packaging Technology with One AI Chip and Four Memory Chips for Internet of Things Modules

“…The FOWLP fabrication process is made up of three basic flows. [14][15][16] Figure 2 shows a simplified image of the manufacturing process flows: The electrical connections between the die and package are implemented by direct RDL formation on the die pad in a die-first (facedown) process; [17,18] RDL formation is performed after CMP using a die-first (face-up) process; [19,20] and flip chip mounting to RDL is performed using solder bumps on the chip in an RDL-first process. [21,22] In this study, a die-first (face-down) process is selected as the manufacturing process because the corresponding mass production technology has already been established.…”