Development of a Validation System based on Formal Description Techniques: Application to an Ada Run Time System

Abstract

In December 1996, a project called LV ARTS was finished and delivered to the ESA. The goal was to validate a real system, namely ATAC, an ADA coprocessor chip, running on a real board. The system was big enough to develop specific methodologies and tools, which are described in this paper. LOTOS was chosen to formally specify AT AC. The formal specification was used to produce test cases that were executed against the chip, after a completion process to obtain executable test cases.