Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448

Pignol, M.; Parrain, Thierry; Claverie, V.; Boleat, C.; Estaves, Guy

doi:10.1109/iolts.2008.24

Cited by 5 publications

(4 citation statements)

References 3 publications

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“…In our research, however, we seek to deliver strong fault coverage for general purpose computing, and aim to efficiently protect even larger and more complex modern application processors, such as those widely used in mobile market and embedded devices. Mobile market processors can run at gigahertz clock rates, for which hardware-side voting or instruction-level lockstep are non-trivial, hence, hardware voting approaches have been implemented only at lower clock rates [15], [17], [18]. For comparison, today's highly optimized COTS library IP achieves clock speeds comparable to traditional FT-processor designs on ASIC even on an FPGA, without requiring manual fine-tuning.…”

Section: Related Workmentioning

confidence: 99%

Dynamic Fault Tolerance Through Resource Pooling

Fuchs

Murillo

Plaat

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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Miniaturized satellites are currently not considered suitable for critical, high-priority, and complex multi-phased missions, due to their low reliability. As hardware-side fault tolerance (FT) solutions designed for larger spacecraft can not be adopted aboard very small satellites due to budget, energy, and size constraints, we developed a hybrid FT-approach based upon only COTS components, commodity processor cores, library IP, and standard software. This approach facilitates fault detection, isolation, and recovery in software, and utilizes fault-coverage techniques across the embedded stack within a multiprocessor system-on-chip (MPSoC). This allows our FPGA-based proofof-concept implementation to deliver strong fault-coverage even for missions with a long duration, but also to adapt to varying performance requirements during the mission. The operator of a spacecraft utilizing this approach can define performance profiles, which allow an on-board computer (OBC) to trade between processing capacity, fault coverage, and energy consumption using simple heuristics. The software-side FT approach developed also offers advantages if deployed aboard larger spacecraft through spare resource pooling, enabling an OBC to more efficiently handle permanent faults. This FT approach in part mimics a critical biological system's ability to tolerate faults, adapt to permanent failure, and enables graceful aging of an MPSoC.

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Section: Related Workmentioning

confidence: 99%

Dynamic Fault Tolerance Through Resource Pooling

Fuchs

Murillo

Plaat

et al. 2018

2018 NASA/ESA Conference on Adaptive Hardware and Systems (AHS)

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“…But to achieve FT using hardware-side measures, arrays of synchronized high-frequency voters or core-lockstepping in hardware are necessary. As voting and corelevel lockstepping at GigaHertz clock rates is non-trivial, it has been implemented only at considerably lower frequencies with non-COTS hardware [9], [11]- [13]. In general, hardware-voting based MPSoC designs are static and non-adaptive, as the entire design's fault-coverage properties are highly chip specific [14].…”

Section: Related Workmentioning

confidence: 99%

Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft

Fuchs

Stefanov

Murillo

et al. 2017

2017 IEEE 26th Asian Test Symposium (ATS)

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Modern embedded technology is a driving factor in satellite miniaturization, contributing to a massive boom in satellite launches and a rapidly evolving new space industry. Miniaturized satellites, however, suffer from low reliability, as traditional hardware-based fault-tolerance (FT) concepts are ineffective for on-board computers (OBCs) utilizing modern systems-on-a-chip (SoC). Therefore, larger satellites continue to rely on proven processors with large feature sizes. Software-based concepts have largely been ignored by the space industry as they were researched only in theory, and have not yet reached the level of maturity necessary for implementation. We present the first integral, real-world solution to enable fault-tolerant general-purpose computing with modern multiprocessor-SoCs (MPSoCs) for spaceflight, thereby enabling their use in future high-priority space missions. The presented multi-stage approach consists of three FT stages, combining coarse-grained thread-level distributed self-validation, FPGA reconfiguration, and mixed criticality to assure long-term FT and excellent scalability for both resource constrained and critical high-priority space missions. Early benchmark results indicate a drastic performance increase over state-of-the-art radiation-hard OBC designs and considerably lower software-and hardware development costs. This approach was developed for a 4-year European Space Agency (ESA) project, and we are implementing a tiled MPSoC prototype jointly with two industrial partners.

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“…The DT2 architecture has been partially validated during the TAFT1 study, and the current CNES TAFT2 R&D study will validate the DMT-NG (New Generation) and the full DT2 architectures [15].…”

Section: E Structural Duplexmentioning

confidence: 99%

COTS-based applications in space avionics

Pignol¹

2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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The use of commercial electronic components is increasingly attractive for the space domain. This paper discusses the current degree of use of these components in space avionics, the selection and qualification phases to be successfully completed before they can be used, and an overview of the constraints the designers of hardware and software architectures have to face regarding these components, with the corresponding solutions. Concerning the issue of upsets, this paper describes possible solutions at architecture and system level and illustrates them with real examples that have already flown or are being developed. The constraints inherent in space avionics do not allow the total performance range of commercial electronic components to be fully exploited; nevertheless, these components -and particularly microprocessors, on which this paper focusesare among the technologies having a potential disruptive capability for future space missions.

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Development of a Testbench for Validation of DMT and DT2 Fault-Tolerant Architectures on SOI PowerPC7448

Cited by 5 publications

References 3 publications

Dynamic Fault Tolerance Through Resource Pooling

Dynamic Fault Tolerance Through Resource Pooling

Bringing Fault-Tolerant GigaHertz-Computing to Space: A Multi-stage Software-Side Fault-Tolerance Approach for Miniaturized Spacecraft

COTS-based applications in space avionics

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