Development of a resource-efficient FPGA-based neural network regression model for the ATLAS muon trigger upgrades

Abstract

This paper reports on the development of a resource-efficient FPGA-based neural network regression model for potential applications in the future hardware muon trigger system of the ATLAS experiment at the Large Hadron Collider (LHC). Effective real-time selection of muon candidates is the cornerstone of the ATLAS physics programme. With the planned ATLAS upgrades for the High Luminosity LHC, an entirely new FPGA-based hardware muon trigger system will be installed that will process full muon detector data within a 10 $${\upmu }\text {s}$$ μ s latency window. The large FPGA devices planned for this upgrade should have sufficient spare resources to allow deployment of machine learning methods for improving identification of muon candidates and searching for new exotic particles. Our neural network regression model promises to improve rejection of the dominant source of background trigger events in the central detector region, which are due to muon candidates with low transverse momenta. This model was implemented in FPGA using 157 digital signal processors and about 5000 lookup tables. The simulated network latency and deadtime are 122 and 25 ns, respectively, when implemented in the FPGA device using a 320 MHz clock frequency. Two other FPGA implementations were also developed to study the impact of design choices on resource utilisation and latency. The performance parameters of our FPGA implementation are well within the requirements of the future muon trigger system, therefore opening a possibility for deploying machine learning methods for future data taking by the ATLAS experiment.

Advances in nuclear detection and readout techniques

“…In addition, column-parallel ADCs have also been developed for MAPS in [511,512] for on-chip data processing. [513] and [514] present the PulseDL AISCs, a system-on-chip for extracting time and energy from the scintillator detector pulses with deep learning. The PulseDL can process one-dimensional pulse signals for classification or regression tasks.…”

“…FPGA can be programmed with either Hardware Description Languages (HDL) or High-Level Synthesis (HLS). The hls4ml is a powerful tool that can [514] translate machine learning tools into HLS code for implementation on an FPGA. Figure 116 shows the general working flow of the hls4ml package, where the red part is the usual working flow to build a neural network, and the blue part explains how the hls4ml works.…”

Firmware implementation of a recurrent neural network for the computation of the energy deposited in the liquid argon calorimeter of the ATLAS experiment

“…Neural networks implemented in FPGAs have demonstrated enhanced object reconstruction and identification at trigger level in LHC experiments [7][8][9][10][11]. The use of neural networks improves the energy resolution in the ATLAS LAr calorimeter especially in the low time-gap region as shown in [5].…”

Nanosecond machine learning regression with deep boosted decision trees in FPGA for high energy physics

“…In the past few years, progress in FPGA firmware design for signal-background classification have allowed for the use of more advanced algorithms using ML / AI at level-0 / level-1 [21][22][23][24][25][26][27][28][29][30][31][32][33], typically relegated to the HLT / EF or offline analysis. FPGA firmware design for regression estimates have been developed for experiments at level-0 / level-1 [34][35][36][37][38].…”