Development of a high-performance general purpose neuro-computer composed of 512 digital neurons

Satō, Yoshio; Shibata, Kouichi; Asai, Masataro; Ohki, Masaru; Sugie, M.; Sakaguchi, Takashi; Hashimoto, Michiaki; Kuwabara, Y.

doi:10.1109/ijcnn.1993.717042

Cited by 15 publications

(8 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Onchip trainable neural hardware implementations have also been reported in literature. Most of the reported ones are custom ASIC implementations such as the GRD chip by Murakawa et al [61], on-chip backpropagation implementation of Ayala et al [15], CNAPS by Hammerstrom [62], MY-NEUPOWER by Sato et al [63], and FPNA by Farquhar, et al [66]. FPGA-based implementations of onchip training algorithms have also been reported such as the backpropagation algorithm implementations in [48,49,57,58].…”

Section: Discussionmentioning

confidence: 99%

“…Multiple GRD chips can be connected for a scalable neural architecture. Two commercially available neurochips from the early 1990s, the CNAPS [62] and MY-NEUPOWER [63], support on-chip training. CNAPS was an SIMD array of 64 processing elements per chip that are comparable to low precision DSPs and was marketed commercially by Adaptive solutions.…”

Section: Designmentioning

confidence: 99%

“…MY-NEUPOWER supported various learning algorithms such as backpropagation, Hopfield, and LVQ and contained 512 physical neurons. The chip performed as a neural computational engine for software package is called NEUROLIVE [63].…”

Section: Designmentioning

confidence: 99%

See 2 more Smart Citations

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Merchant

Peterson

2010

VLSI Design

View full text Add to dashboard Cite

Dedicated hardware implementations of artificial neural networks promise to provide faster, lower-power operation when compared to software implementations executing on microprocessors, but rarely do these implementations have the flexibility to adapt and train online under dynamic conditions. A typical design process for artificial neural networks involves offline training using software simulations and synthesis and hardware implementation of the obtained network offline. This paper presents a design of block-based neural networks (BbNNs) on FPGAs capable of dynamic adaptation and online training. Specifically the network structure and the internal parameters, the two pieces of the multiparametric evolution of the BbNNs, can be adapted intrinsically, in-field under the control of the training algorithm. This ability enables deployment of the platform in dynamic environments, thereby significantly expanding the range of target applications, deployment lifetimes, and system reliability. The potential and functionality of the platform are demonstrated using several case studies.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Designmentioning

confidence: 99%

See 1 more Smart Citation

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Merchant

Peterson

2010

VLSI Design

View full text Add to dashboard Cite

show abstract

“…Fixed-point arithmetic is often chosen for NN accelerators to produce smaller PEs that can be integrated in large number [11]- [14]. As already mentioned, it has been shown by simulation that the use of fixedpoint variables with an appropriate number of bits does not hinder significantly the convergence of NN algorithms [6].…”

Section: Fixed-point Arithmeticmentioning

confidence: 99%

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Ienne

Viredaz

1995

Journal of VLSI Signal Processing

View full text Add to dashboard Cite

Abstract.A systolic array of dedicated processing elements (PEs) is presented as the heart of a multi-model neural-network accelerator. The instruction set of the PEs makes possible to implement several widely-used neural models, including multi-layer Perceptrons with the back-propagation learning rule and Kohonen feature maps. Each PE holds an element of the synaptic weight matrix. An instantaneous swapping mechanism for the weight matrix makes the efficient implementation of neural networks larger than the physical PE array possible. A systolicallyflowing instruction accompanies each input vector propagating in the array. This avoids the need of emptying and refilling the array when the operating mode of the array is changed. Fixed point arithmetic is used in the PE. The problem of optimally scaling real variables in fixed-point format is addressed.Both the GENES IV chip, containing a matrix of 2 • 2 PEs, and an auxiliary arithmetic circuit have been manufactured and successfully tested. The MANTRA I machine has been built around these chips. Peak performances of the full system are between 200 and 400 MCPS in the evaluation phase and between 100 and 200 MCUPS during the learning phase (depending on the algorithm being implemented).

show abstract

“…We have also succeeded in developing a neuro-computer that has a high-speed learning function [Sato 19931. Making the most of that experience, we here propose new microprocessorbased evolvable hardware.…”

Section: Introductionmentioning

confidence: 98%

Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory

Sato

Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546)

Self Cite

View full text Add to dashboard Cite

A new idea for evolvable hardware based on a microprocessor is proposed. Evolvable hardware is a new direction in hardware research that fuses evolutionary computation and reconfigurable logic LSI circuits. In recent years, there has been much research using Programmable Logic Devices (PLD) and Field Programmable Gate Arrays (FPGA). In particular, the application of digital circuit evolution to engineering fields has already begun. On the other hand, long learning time, difficulty to predict when an effective capability will appear, large chip size and other such problems have hindered progress in diffusion into engineering fields. Here, we propose register transfer level evolution performed on a microprocessor as a means of addressing these problems. Specifically, we propose (1) incorporating flash memory into the microprocessor to allow on-board programming and reprogramming, (2) using genetic algorithms to provide a register transfer level learning capability, and (3) the use of a framework that provides for the coexistence of static programs and programs that self-organize through learning. On the basis of a simple hand-design, we concluded that the proposed method is more effective in terms of learning efficiency and reliability than the conventional approach using FPGA and PLD.

show abstract

Development of a high-performance general purpose neuro-computer composed of 512 digital neurons

Cited by 15 publications

References 3 publications

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

Evolvable Block-Based Neural Network Design for Applications in Dynamic Environments

GENES IV: A bit-serial processing element for a multi-model neural-network accelerator

Proposal for a field-evolvable hardware based on a microprocessor incorporated flash memory

Contact Info

Product

Resources

About