Development of a fabrication technology for double-sided AC-coupled silicon microstrip detectors

Betta, G.-F. Dalla; Boscardin, M.; Bosisio, L.; Rachevskaia, I.; Zen, M.; Zorzi, N.

doi:10.1016/s0168-9002(00)01068-8

Search citation statements

Order By: Relevance

Paper Sections

Select...

Technological Aspects1

Detector Hardware1

Citation Types

Supporting

Mentioning

Contrasting

Year Published

2004

2023

Publication Types

Select...

Article6

Book1

Relationship

Self Cite0

Independent7

Authors

Journals

Cited by 22 publications

(2 citation statements)

References 9 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Alternative bias techniques are based on punch-through or integrated transistors (the so-called FOXFET) [2]. Needless to say, double-sided detectors involve a higher complexity as compared to single-sided ones, since both sides of the wafers must be patterned and processed [44]. One evident need is double-side alignment of different layers, calling for special lithography equipment.…”

Section: Technological Aspectsmentioning

confidence: 99%

Silicon Radiation Detector Technologies: From Planar to 3D

Betta

2023

Chips

View full text Add to dashboard Cite

show abstract

Section: Technological Aspectsmentioning

confidence: 99%

Silicon Radiation Detector Technologies: From Planar to 3D

Betta

2023

Chips

View full text Add to dashboard Cite

show abstract

“…A test-station for silicon microstrip detectors has been set up. The sensor utilized is a doublesided silicon strip detector [1] with dimensions of 2 × 2 cm 2 , a strip pitch of 50 ñm, punch-through biasing and AC coupled contact pads. The sensor is mounted on an L-shaped PCB displayed in figure 1.…”

Section: Detector Hardwarementioning

confidence: 99%

FPGA-based readout for double-sided silicon strip detectors

Becker¹,

Brinkmann²,

Koop³

et al. 2011

J. Inst.

View full text Add to dashboard Cite

This work presents an FPGA-based readout system for double-sided silicon strip sensors based on the APV25 front-end chip. The system consists of an ADC-card and a digital readout board containing an FPGA. Data extraction algorithms implemented in the FPGA allow baseline and pedestal correction, hit detection and event-building. These algorithms represent an efficient data reduction tool and provide high readout rates. Details of the system, the algorithms applied and performance will be discussed featuring data collected in various tests experiments.

show abstract