Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

Gao, Wu; Gao, Bo; Li, X.; Wei, Tingcun; Gao, Deyuan; Hu, Y.

doi:10.1016/j.nima.2014.12.083

Cited by 15 publications

(8 citation statements)

References 15 publications

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“…In our previous work [5], a compact radiation-hardened low-noise front-end readout ASIC including the CSA and pulse shaper was designed. In this paper, we focus on the design of a high-resolution high-speed ADC.…”

Section: Jinst 13 P02027mentioning

confidence: 99%

“…In this paper, we focus on the design of a high-resolution high-speed ADC. From [5], the energy range of the detected X-ray is from 1.45 keV to 281 keV and the gain is 115 mV/fC as the shaping time is 1.5 µs. The minimum energy identified and quantized by the subsequent ADC is 0.3 keV.…”

Section: Jinst 13 P02027mentioning

confidence: 99%

“…The output voltage of the shaper is sampled by a high-speed ADC. In our solution, at least eight voltage values of the shaped pulse are sampled and digitized [5][6][7]. The data from the ADC is collected by a programmable FPGA which can run an algorithm to calculate the peak value of the shaped pulse.…”

Section: Introductionmentioning

confidence: 99%

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Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

et al. 2018

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This paper presents a 12-bit pipelined successive approximation register (SAR) ADC for CZT-based hard X-ray Imager. The proposed ADC is comprised of a first-stage 6-bit SAR-based Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. A novel MDAC architecture using Vcm-based Switching method is employed to maximize the energy efficiency and improve the linearity of the ADC. Moreover, the unit-capacitor array instead of the binary-weighted capacitor array is adopted to improve the conversion speed and linearity of the ADC in the first-stage MDAC. In addition, a new layout design method for the binary-weighted capacitor array is proposed to reduce the capacitor mismatches and make the routing become easier and less-time-consuming. Finally, several radiation-hardened-by-design technologies are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 μm mixed-signal 1.8V/3.3V process and operated at 1.8 V supply. The chip occupies a core area of only 0.58 mm2. The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 66.7 dB and a peak spurious-free dynamic range (SFDR) of 78.6 dB at 10 MS/s sampling rate and consumes 10 mW. The figure of merit (FOM) of the proposed ADC is 0.56 pJ/conversion-step.

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Section: Jinst 13 P02027mentioning

confidence: 99%

Section: Jinst 13 P02027mentioning

confidence: 99%

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Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

et al. 2018

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“…The TSMC 0.35 µm CMOS process is used in the front-end readout chips developed in our laboratory [21] to extend the voltage dynamic range. These front-end readout chips can tolerate TID effects up to 200 krad according to experimental verification.…”

Section: Radiation-hardened Designmentioning

confidence: 99%

A 12-bit, 1 MS/s SAR-ADC for a CZT-based multi-channel gamma-ray imager using a new digital calibration method

et al. 2016

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The successive approximation register-analog to digital converter (SAR-ADC) is widely used in the CdZnTe-based gamma-ray imager because of its outstanding characteristics of low power consumption, relatively high resolution, and small die size. This study proposes a digital bit-by-bit calibration method using an input ramp signal to further improve the conversion precision and power consumption of an SAR-ADC. The proposed method is based on the sub-radix-2 redundant architecture and the perturbation technique. The proposed calibration algorithm is simpler, more stable, and faster than traditional approaches. The prototype chip of the 12-bit, 1 MS/s radiation-hardened SAR-ADC has been designed and fabricated using the TSMC 0.35 µm 2P4M CMOS process. This SAR-ADC consumes 3 mW power and occupies a core area of 856 × 802µm 2 . The digital bit-by-bit calibration algorithm is implemented via MATLAB for testing flexibility. The effective number of bits for this digitally calibrated SAR-ADC reaches 11.77 bits. The converter exhibits high conversion precision, low power consumption, and radiation-hardened design. Therefore, this SAR-ADC is suitable for multi-channel gamma-ray imager applications.

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“…In our Laboratory, some designers focused on the design of front-end readout ASICs. A series of front-end readout ASIC prototypes (named as SENSROC) have been designed and fabricated [4][5][6]. For integrating the front-end readout circuit and ADC on one chip, a special ADC for CZT-based imaging system is urgently needed.…”

Section: Introductionmentioning

confidence: 99%

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

et al. 2016

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This paper presents a 12-bit 2 MS/s pipelined successive approximation register (SAR) ADC for CZT-based imaging system. The proposed ADC is divided into a first-stage 6-bit SARbased Multiplying Digital Analog Converter (MDAC) and a second-stage 8-bit SAR ADC. The first-stage MDAC has a gain of 16 instead of the usual gain of 64, which considerably minimizes the power dissipation of residue amplifier. The second-stage 8-bit SAR ADC employs unit bridge capacitor split-capacitor architecture aiming to reduce the load capacitance of residue amplifier so as to minimize the power dissipation of the proposed ADC. Moreover, a code-randomized calibration algorithm is proposed to improve the linearity of the second-stage 8-bit split-capacitor SAR ADC. In addition, several radiation-hardened-by-design techniques are adopted in the layout design against space radiation effects. The prototype chip was fabricated in 0.18 µm mixed-signal 1.8 V/3.3 V process and occupied a core area of 0.71 mm 2 . The proposed pipelined SAR ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 63.2 dB at 2 MS/s sampling rate and consumes 12 mW power in total. The figure of merit (FoM) of the proposed ADC is 5.06 pJ/conversion-step. K: Data acquisition circuits; Front-end electronics for detector readout; Radiation damage to electronic components 1Corresponding author.

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Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

Cited by 15 publications

References 15 publications

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

Design and characterization of a 12-bit 10MS/s 10mW pipelined SAR ADC for CZT-based hard X-ray imager

A 12-bit, 1 MS/s SAR-ADC for a CZT-based multi-channel gamma-ray imager using a new digital calibration method

Design of a 12-bit 2 MS/s 12 mW pipelined SAR ADC in CMOS 0.18 μm technology for CZT-based imaging system

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