Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

Leon, Vasileios; Stamoulias, Ioannis; Lentaris, George; Soudris, Dimitrios; Gonzalez-Arjona, David; Domingo, Ruben; Codinachs, David Merodio; Conway, Isabelle

doi:10.1109/access.2021.3114502

Cited by 11 publications

(1 citation statement)

References 20 publications

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“…Unfortunately, they have yet to be used for on-board AI acceleration. Excluding the NG-ULTRA, an extensive survey on NanoXplore FPGAs can be found in the literature, investigating the portability of Computer Vision (CV) and Digital Signal Processing (DSP) hardware IPs on these devices [34]. However, a thorough study to assess the portability of GPGPU and AI hardware accelerators is still missing.…”

Section: A Technology Independencementioning

confidence: 99%

Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications

Monopoli,

Zulberti,

Nannipieri

et al. 2023

2023 European Data Handling &Amp; Data Processing Conference (EDHPC)

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Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhead, power consumption, and fault-tolerant solutions. In this particular scenario, soft General-Purpose Computing on Graphic Processing Units has the potential to revolutionise space-related activities. Indeed, by leveraging both Field Programmable Gate Array technology and Graphic Processing Unit computing, it becomes feasible to achieve highperformance capabilities without compromising neither power consumption nor radiation tolerance features. Moreover, the use of reconfigurable hardware can facilitate the acceleration of a wide range of Machine Learning algorithms, avoiding the drawbacks of excessive specialisation. This paper explores the State-of-the-Art in terms of hardware platforms for on-the-edge acceleration of Artificial Intelligence algorithms and compares it with a possible System-on-Chip implementation based on a soft-Graphic Processing Unit. Then, the attention is shifted towards the investigation of key aspects for future space missions, such as reliability and Dynamic Partial Reconfiguration. We point out the lack of European technological solutions, emphasising the promising potential offered by NanoXplore devices. We also discuss the importance of fault detection and mitigation techniques in space applications, covering the most commonly employed hardware methods for reliability enhancement and highlighting the lack of work in the field of General-Purpose Computing for Graphic Processing Units, especially in the space sector. Furthermore, we briefly examine the implementation of Dynamic Partial Reconfiguration over a System-on-Chip featuring a soft-Graphic Processing Unit IP. Finally, in the last section of the paper, we hint at future development of the project and conclude the work.

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Section: A Technology Independencementioning

confidence: 99%

Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications

Monopoli,

Zulberti,

Nannipieri

et al. 2023

2023 European Data Handling &Amp; Data Processing Conference (EDHPC)

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Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC

Pagonis,

Leon,

Soudris

et al. 2023

Applied Reconfigurable Computing. Architectures, Tools, and Applications

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HW/SW co-design on embedded SoC FPGA for star tracking optimization in space applications

Panousopoulos,

Papaloukas,

Leon

et al. 2024

J Real-Time Image Proc

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Star trackers are crucial for satellite orientation. Improving their efficiency via reconfigurable COTS HW accommodates NewSpace missions. The current work considers SoC FPGAs to leverage both increased reprogramming and high-performance capabilities. Based on a custom sensor+FPGA system, we develop and optimize the algorithmic chain of star tracking by focusing on the acceleration of the image processing parts. We combine multiple circuit design techniques, such as low-level pipelining, word-length optimization, HW/SW co-processing, and parametric HLS+HDL coding, to fine-tune our implementation on Zynq-7020 FPGA when using real and synthetic input data. Overall, with 4-MPixel images, we achieve more than 24 FPS throughput by accelerating >95% of the computation by 8.9$$\times$$ × , at system level, while preserving the original SW accuracy and meeting the real-time requirements of the application.

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Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks

Cited by 11 publications

References 20 publications

Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications

Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications

Increasing the Fault Tolerance of COTS FPGAs in Space: SEU Mitigation Techniques on MPSoC

HW/SW co-design on embedded SoC FPGA for star tracking optimization in space applications

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