Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration

Wang, Fei; Han, Liqiang; Theuwissen, Albert

doi:10.1109/jssc.2018.2856252

Cited by 18 publications

(25 citation statements)

References 20 publications

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“…There are 14 groups of different pixel designs with various conversion gain and noise performances, which makes the photon response non-uniform. Table I summarizes the performance of the proposed CIS and compares it with prior art in terms of linearity [3]- [9]. The nonlinearity of this CIS is 2× better than the state-of-the-art.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…The nonlinear transfer function between the number of incoming photons and the final digital output (DO) of the ADC is stored in the SRAM. The SRAM data is then used to pre-distort the ADC's ramp in such a way that the resulting ADC nonlinearity compensates for the nonlinear behavior of the CIS [3].…”

Section: The Calibration Algorithmmentioning

confidence: 99%

“…To improve the circuit efficiency and reduce the following calculation tasks on soft-level, many linearity optimization efforts have also been spent on chip-level, either from the pixel or the circuit standpoint [3]- [4]. Most of the inherent pixel's nonlinearity is caused by the nonlinear gain of the source follower (SF) and by the voltage dependency of the integration capacitor on the floating diffusion region(CFD) [5].…”

Section: Introductionmentioning

confidence: 99%

“…Most of the inherent pixel's nonlinearity is caused by the nonlinear gain of the source follower (SF) and by the voltage dependency of the integration capacitor on the floating diffusion region(CFD) [5]. A novel pixel design is proposed in [3], which uses a single stage operational amplifier (OPA) instead of the conventional source follower, to drive the load circuits. This type of pixel structure can avoid the introduction of the SF's nonlinearity.…”

Section: Introductionmentioning

confidence: 99%

“…In [3], we also developed an on-chip digital calibration method to improve the linearity of the CIS from the system level. By calibrating the ramp signal of the ADC, the pixels can achieve a nonlinearity less than 0.06% after calibration.…”

Section: Introductionmentioning

confidence: 99%

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Two calibration methods to improve the linearity of a CMOS image sensor

Wang¹,

Theuwissen²

2018

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This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 × 128 pixel sensor with a size of 10 μm×12 μm is fabricated using a 0.18 μm 1P4M CIS process. Both calibration methods show obvious improvement on the linearity of the CIS. Compared with the voltage mode (VM) calibration, the pixel mode (PM) calibration method achieves better linearity results by improving the nonlinearity of the CIS 26×. This results in a minimum nonlinearity of 0.026%, which is a 2× better than the state-of-the-art.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: The Calibration Algorithmmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Two calibration methods to improve the linearity of a CMOS image sensor

Wang¹,

Theuwissen²

2018

Self Cite

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A multipurpose circuit to read out and digitize pixel signal for low‐power CMOS imagers

Teymouri

2020

Circuit Theory & Apps

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Summary A complementary metal oxide semiconductor (CMOS) image sensor with a resolution of 128 × 128 pixels is presented in this paper in which pixel signal readout, noise suppression, and comparing operations are performed by one circuit during two steps: reading and conversion. The main idea of this work is to combine three main operations of an image sensor in one circuit. This method helps to decrease power consumption, silicon area, total noise, and imaging time. The total power consumption of the imager is 11 mW with a 2.5‐V power supply and 40‐fps frame rate. The pixel layout size is 10 × 10 μm2 with a fill‐factor of 81%. The analog to digital converter (ADC) resolution is 10 bits, and the error resulted from the proposed circuit is about ±0.5 least significant bit (LSB). The proposed CMOS image sensor was designed based on Taiwan Semiconductor Manufacturing Company (TSMC) 0.18‐μm CMOS technology and was simulated by CADENCE SPECTRE circuit simulator. This circuit can be proposed for a CMOS imager with highly accurate and efficient power consumption.

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A 256 × 256 CMOS image sensor with differential readout and data converter circuits

Karamzadeh

Teymouri

Dousti

et al. 2023

Circuit Theory & Apps

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Summary In this paper, a 256 × 256 CMOS image sensor is introduced in which the pixel signals are read and converted into digital data in a completely differential mode. This technique helps to obtain pixel signals with higher linearity and accuracy compared with conventional methods. Improving the linearity and accuracy of the image sensor has a direct impact on increasing the quality of the generated images. The simulation results of the proposed pixel readout circuit show that the THD, SINAD, SNR, and SFDR are 0.45%, 47 dB, 66 dB, and 46 dB, respectively. The voltage gain of the proposed readout circuit is about 1, causing it to read the photodetector signals more accurately than the conventional methods. A full differential single‐slope ADC with a working frequency of 50 Mhz has the task of converting the pixel signal to 10 bits of digital data. The total power consumption of a column of sensors is about 80 μW. All the circuits are designed and implemented using 0.18‐μm CMOS technology in Virtuoso and simulated by the SPECTRE.

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Development and Evaluation of a Highly Linear CMOS Image Sensor With a Digitally Assisted Linearity Calibration

Cited by 18 publications

References 20 publications

Two calibration methods to improve the linearity of a CMOS image sensor

Two calibration methods to improve the linearity of a CMOS image sensor

A multipurpose circuit to read out and digitize pixel signal for low‐power CMOS imagers

A 256 × 256 CMOS image sensor with differential readout and data converter circuits

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