Development and characterisation of high electrical performances TSV for 3D applications

Henry, David D.; Chéramy, S.; Charbonnier, Jean; Chausse, P.; Neyret, M.; Garnier, G.; Brunet-Manquat, C.; Verrun, S.; Sillon, N.; Bonnot, L.; Farcy, A.; Cadix, L.; Rousseau, M.; Saugier, E.

doi:10.1109/eptc.2009.5416490

Cited by 14 publications

(2 citation statements)

References 6 publications

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“…In addition, the channels in the passive interposer should be standardized to make modular SoC design. Hence, there is increase in research of active interposer [16,4,2,17,18,19,20,21] both in industry and academia. We also consider an active interposer substrate for designing the interposer network.…”

Section: Modular 25d Soc Integrationmentioning

confidence: 99%

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Majumder,

Kim,

Huang

et al. 2019

Preprint

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The increase in design cost and complexity have motivated designers to adopt modular design of System on Chip (SoC) by integrating independently designed small chiplets. However, it introduces new challenges for correctness validation, increasing chances of forming deadlock in the system involving multiple chiplets. Although there have been many solutions available for deadlock freedom in flat networks, the study on deadlock issue in chiplet-based systems is still in its infancy.A recent study suggests adding extra turn restrictions as a viable solution for this problem. However, imposing extra turn restrictions reduces chiplet design flexibility and interposer design complexity. In addition, it may lead to non-minimal route and traffic imbalance forming hotspots, resulting in high latency and low throughput.We propose Remote Control (RC), a simple routing oblivious deadlock avoidance scheme. Our proposal is based on two key observations. First, packets with destinations in the current chiplet are blocked by packets with destinations outside the chiplet. Second, deadlock always involves multiple boundary routers 1 . Hence, we segregate different traffics to alleviate mutual blocking at the chiplet's boundary routers. Along with guarantee of deadlock freedom and performance enhancements, our simple RC scheme also provides more routing flexibility to both chiplet and SoC designers, as compared to the state-of-the-art.

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Section: Modular 25d Soc Integrationmentioning

confidence: 99%

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Majumder,

Kim,

Huang

et al. 2019

Preprint

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show abstract

“…The combination of 3D integration and NoC technologies provides a new horizon for on-chip interconnect design. 3D NoC offers higher bandwidth, smaller form factor, shorter wire length, lower power dissipation, and better performance than traditional 2D NoCs [5]. 3D integration by Through-silicon Via (TSV) is currently the most popular choice as a vertical-electrical connection form between tiers which is demonstrated in Fig.…”

Section: Introductionmentioning

confidence: 99%

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip

Eghbal

Yazdi

Bagherzadeh

2014

2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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A reliable Three Dimensional Network-on-Chip (3D NoC) is required for future many-core systems. Through-silicon Via (TSV) is the prominent component of 3D NoC to support better performance and lower power consumption. Inductive TSV coupling has large disruptive effects on Signal Integrity (SI) and transmission delay. In this paper, TSV inductive coupling is analyzed based on technology process, TSV length, and TSV radius for a range of frequencies. A classification of inductive coupling voltage is presented for different TSV configurations. A novel coding technique is devised to mitigate the inductive coupling effects by adjusting the current flow pattern. Simulations for a 4 × 8 TSV matrix show 23% coupled voltage mitigation, imposing 12.5% information redundancy.

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A complete resistance extraction methodology and circuit models for typical TSV structures

Chung

Lwo

et al. 2013

International Journal of Electronics

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Development and characterisation of high electrical performances TSV for 3D applications

Cited by 14 publications

References 6 publications

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

Remote Control: A Simple Deadlock Avoidance Scheme for Modular System on Chip

TSV-to-TSV inductive coupling-aware coding scheme for 3D Network-on-Chip

A complete resistance extraction methodology and circuit models for typical TSV structures

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