Developing parallel architectures for range and image sensors

Abstract

Range Sensors and Feature Extraction We describe a cost-effective method for developing parallel architectures which increase the perjormance of range and image sensors. A parametrised edge detector and its systolic implementation using Field-Programmable Gate Arrays (FPGAs) are presented. Experiments and analyses indicate that our circuits can satisfr the pelfomnce requirements, and some of the designs out-perform the software equivalent on a 486-based PC by nearly two orders of magnitude.