Developing method of vector synthesis deductive logic forcomputer systems fault analysis

Abstract

The article is devoted to the development of models and methods for fault analysis for examinate test patterns. Deductive fault simulation of digital devices is the most advanced technology that serves the field of design and testing of modern computer systems. At the same time, fault simulation solves the problem of assessing the quality of the test in the class of single constant defects. However, the computational complexity of obtaining deductive formulas, estimated as n3 , is a rather difficult task for high-dimensional RTL-level functional circuits, so the deductive method is usually used only for digital circuits represented at the gate level. Next, we propose a vector method for synthesis deductive formulas for digital schemes represented by RTL elements. This method became possible due to the element description of any complexity in the form of output states vector for combinational device. The model of xor-relationships between the wonderful logical functions (or, xor, and) of digital objects is improved, which is convoluted into zero-space. It makes possible to solve the problems of design and test, machine learning, search for similarities-differences, and destructive components in processes and phenomena. The advantages of the vector model for a compact description of objects, functions and structures are determined. It is proposed to replace analytical expressions that require algorithmically complex calculating, with vector data structures for describing functional logic. Vector-deductive method for synthesis formulas for transporting input fault lists is proposed. It has a quadratic computational complexity of register operations. The coordinate-vector model of defects is considered, not tied to input variables, which can be used for efficient processing of complex logic circuits when assessing the quality of synthesized tests. An algorithm for the synthesis of deductive vectors is presented, which differs from the known ones in the technological parallel processing simplicity of truth tables and makes it possible to create structural and logical conditions for simulating faults in digital projects of the gate, register and system description levels. An efficient method for the synthesis of a deductive truth table according to the rule L=T⊕F is proposed. It differs from the known ones by using vector-coordinate parallel xor-operation. It provides the transportation of faults through a functional element of arbitrary complexity.

Vector-deductive Memory-based Transactions for Fault-as-address Simulation

“…In this case, the matrix (table) and the vector are two forms for describing models that pass into each other. A vector (binary, multi-valued) is a compact form of a truth table in the form of an ordered sequence of output states, if the input address components are sorted in ascending order [7][8][9][10][11][12][13]. The matrix, if necessary, expands into a one-dimensional vector for the convenience of parallel data processing in register memory.…”

“…Parallelism in solving combinatorial problems is a physical property of quantum computing, which in classical computing for parallel fault simulation and fault diagnosis is provided by unitarily encoded data structures due to redundant memory [7,11,16,18]. The topic is of particular interest in the field of design and test from researchers involved in testing [1] and verification of digital systems-on-chips in the emerging technology of nanoelectronics.…”

“…• High computational complexity of combinatorial analysis algorithms at the register level of model description [2,[4][5][6][7][14][15][16][17][18][19][20][21][22].…”

“…The essence of deductive simulation is to change the logic of the element F depending on the input conditions T. Deductive modeling, proposed exactly 50 years ago by Armstrong [26], is still the most elegant and effective tool for analyzing the quality of tests and synthesizing tables for detecting faults, tracing the propagation paths of the fault. Further, its implementation is proposed based on the vector form of logic description [7][8][9][10][11][12][13], which excludes logical analytical forms. This makes it possible to significantly simplify the algorithms for the synthesis of deductive models and their application for interpretative simulation of digital elements and large-scale circuits.…”

“…A new method for synthesizing deductive formulas is based on a vector definition of or-element (in this case) and presented in the following table (Fig. 2, a) [7].…”