Developing hardware-based applications using presence-2

Weeks, Michael; Freeman, Michael; Moulds, Anthony; Austin, Jim

doi:10.1049/ic.2005.0792

Cited by 4 publications

(2 citation statements)

References 4 publications

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“…AURA The AURA provides a range of classes and methods for rapid partial matching of large data sets [A95]. AURA may be implemented using a C++ software library or using proprietary hardware coupled with a dedicated embedded C++ library [WFMA05]. AURA has been used in an information retrieval system [H01], high-speed rule matching systems [AKL95], 3-D structure matching [TA00] and trademark searching [AA98].…”

Section: 1mentioning

confidence: 99%

A binary neural shape matcher using Johnson Counters and chain codes

2009

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Images may be matched as whole images or using shape matching. Shape matching requires: identifying edges in the image, finding shapes using the edges and representing the shapes using a suitable metric. A Laplacian edge detector is simple and efficient for identifying the edges of shapes. Chain codes describe shapes using sequences of numbers and may be matched simply, accurately and flexibly. We couple this with the efficiency of a binary associative-memory neural network. We demonstrate shape matching using the neural network to index and match chain codes where the chain code elements are represented by Johnson codes

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Section: 1mentioning

confidence: 99%

A binary neural shape matcher using Johnson Counters and chain codes

2009

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“…The growing applicability of artificial neural networks (ANNs) to solve problems related to complex real-time fields such as image and signal processing [1][2][3] results from their massive parallelism, perfect generics and learning capacities. Intensive ANN computing requires a great-power use to solve these problems.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Implementation of a low‐power LVQ architecture on FPGA

Najoua

Boubaker

Bedoui

2017

IET Circuits, Devices & Syst

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This study presents an architecture-optimising methodology for embedding an learning vector quantization (LVQ) neural network on an field programmable gate array (FPGA) device. The embedded architecture contains both learning and decision circuitry and is optimised towards the lowest power/energy consumption. The low-power/energy architecture is obtained through the selection of the best one amongst a number of architectures produced by FPGA software design tools that combine power, area and the ergonomic utilisation of internal FPGA resources. A complete characterisation of power at the architectural level was carried out using the Xpower tool. An analytical power model was determined by the following parameters: area, delay and LVQ topology. Concerning the authors' architecture, there is a 28% gain in the area design. Moreover, it consumes 8% power in the nanoboard 3000 compared with the other ones.

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Introduction

Ansari

2013

Non-Linear Feedback Neural Networks

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Developing hardware-based applications using presence-2

Cited by 4 publications

References 4 publications

A binary neural shape matcher using Johnson Counters and chain codes

A binary neural shape matcher using Johnson Counters and chain codes

Implementation of a low‐power LVQ architecture on FPGA

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