“…Clearly, Equation (13) implies that the e int state has a strong connection to the voltage regulation error e v , particularly with its transient behaviour, which is also corroborated via empirical evidence. In order to illustrate this connection and at the same time help explain the integrator resetting (IR) mechanism, consider Figure 12, where the following experiment is performed: the load signal S 1 (5 kW, 30 kW, m, t − t 0 ) is applied, followed by a second load signal, S 2 (30 kW, 5 kW, m, t − (t 0 þ d)), with t 0 = 0.2 s, m ¼ 1 kW ms and d = 15 ms. We are mainly interested in what happens at the beginning of the second load signal starting at time t 1 = t 0 þ d, and the subsequent development.…”