Developing a low-cost high-quality software tool for dynamic fault-tree analysis

Dugan, J.B.; Sullivan, Kevin; Coppit, David

doi:10.1109/24.855536

Cited by 145 publications

(68 citation statements)

References 20 publications

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“…However, especially in programmable systems, situations frequently arise in which the order of events is vital for the correct or faulty behavior of systems (Dugan, 1999), (Bozzano and Villafiorita, 2003). In general, the representation of controller faults in fault trees requires mechanisms for specifications of temporal relationships among events.…”

Section: Methods Overviewmentioning

confidence: 99%

Obtaining temporal and timed properties of logic controllers from fault tree analysis

Santiago¹,

Roth²,

Faure³

2006

Information Control Problems in Manufacturing 2006

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One of the prerequisites for formal verification of logic controllers using modelchecking is the formalization of properties to verify. The work presented in this paper proposes a method to elaborate the formal properties of a logic controller from a Fault Tree Analysis (FTA). The method developed here extends the traditional FTA with event ordering and timed information by introducing specific gates which model logic and physical time constraints. The behavior of these gates is then formalized in the form of state automata; formal properties are derived from the set of automata obtained at the end of FTA. A simple case study exemplifies the method.

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Section: Methods Overviewmentioning

confidence: 99%

Obtaining temporal and timed properties of logic controllers from fault tree analysis

Santiago¹,

Roth²,

Faure³

2006

Information Control Problems in Manufacturing 2006

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show abstract

“…This requires the use of gates which have come to be known as "dynamic". Some of them modeling functional dependencies and primary-spare behavior have been proposed by (Dugan, 1999).…”

Section: Describing Systematic Faults Using a Vocabulary Of Gatesmentioning

confidence: 99%

Including Systematic Faults Into Fault Tree Analysis

Santiago

Faure

Papadopoulos

2006

IFAC Proceedings Volumes

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Fault Tree Analysis (FTA) is a technique widely used for fault forecasting of physical systems. Although FTA is considered a well established safety analysis technique, paradoxically classical Fault Trees include only random faults. However, in modern automated systems, undesirable events arise not only from random hardware faults but also from defects in the logic of software controllers that control the physical system. Faults generated by these software controllers are systematic faults caused by coding errors or misinterpretations of control requirements. This paper proposes an extension to the basic Fault Trees construction process which takes into account this category of faults and advocates the use of dynamic and temporal gates to model it.

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“…In order to solve this problem, Dugan [10][11][12] proposed a new method for reliability analysis-Dynamic fault tree analysis. The method introduces a series of dynamic logic gates to describe the failure behavior of the system on timing rules and dynamic.…”

Section: The Dynamic Logic Gatementioning

confidence: 99%