Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions

Suman, P. Vijay; Pandya, Paritosh K.

doi:10.1007/978-3-642-00982-2_62

Cited by 3 publications

(7 citation statements)

References 8 publications

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“…As the main result of this paper, we show that starting with an IRTA A, we can obtain a determinized one clock IRTA B whose size is doubly exponential in the size of A. Comparing this result to the earlier works of [12], [13] and [5] we note the following.…”

Section: Introductionsupporting

confidence: 63%

“…[12] gives a technique for obtaining a language equivalent determinized one clock IRTA A ′ from an IRTA A, with a triply exponential blow up in the number of locations. Subsequently, [13] proposes a technique to obtain from an IRTA or ǫ-IRTA A, a one clock ǫ-IRTA, with a doubly exponential blow up in the number of locations. The result in [13] cannot be considered an improvement over the one in [12] since the final IRTA obtained has ǫ-moves (even when we start with an IRTA without ǫ-moves).…”

Section: Introductionmentioning

confidence: 99%

“…Subsequently, [13] proposes a technique to obtain from an IRTA or ǫ-IRTA A, a one clock ǫ-IRTA, with a doubly exponential blow up in the number of locations. The result in [13] cannot be considered an improvement over the one in [12] since the final IRTA obtained has ǫ-moves (even when we start with an IRTA without ǫ-moves). The determinization technique suggested in [5] applied to an IRTA A, gives a deterministic timed automaton B (not an IRTA), whose size is doubly exponential in the size of A, and which has ≤ c m + 1 clocks, where c m is the biggest constant used in the guards of A.…”

Section: Introductionmentioning

confidence: 99%

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Integer Reset Timed Automata: Clock Reduction and Determinizability

Manasa,

2010

Preprint

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In this paper, we propose a procedure that given an integer reset timed automaton (IRTA) A, produces a language equivalent deterministic one clock IRTA B whose size is at most doubly exponential in the size of A. We prove that this bound on the number of locations is tight. Further, if integer resets are used in stopwatch automata, a subclass of stopwatch automata which is closed under all boolean operations and for which reachability is decidable is obtained.

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Section: Introductionsupporting

confidence: 63%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Integer Reset Timed Automata: Clock Reduction and Determinizability

Manasa,

2010

Preprint

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“…The diagnoser can be viewed, in general, as the TA obtained through determinization of the system under study and with respect to the specified observables Σ o and Σ c o . Determinization of TA is an undecidable problem [2,31], except for some classes [4,28,13,25]. In consequence, an algorithm for on-the-fly determinization of a copy of the system with marked faulty locations is generated.…”

Section: Compute a B And Check That ∀ρ ∈ Runsmentioning

confidence: 99%

Designing Systems with Detection and Reconfiguration Capabilities: A Formal Approach

Dragomir

Iosti

Bozga

et al. 2018

Lecture Notes in Computer Science

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The design of functionally correct autonomous systems which operate in an unknown environment and that satisfy reliability, availability, maintainability, and safety (RAMS) requirements is a challenge. In this paper we focus on the detection and reconfiguration features these systems must provide. Indeed, evolving in an unknown environment can invalidate the assumptions made during the design phase. In particular, different hardware components might fail and provide erroneous inputs to the system, which will pass in a degraded mode where the expected RAMS do not hold anymore. Such faults need to be detected as early as possible and reconfiguration strategies must be applied to bring the system back into a nominal mode where the RAMS are satisfied. We propose an automated design process based on formal methods to develop Fault Detection, Isolation and Recovery (FDIR) components targeting partially observable timed systems.We describe how to automatically synthesize runtime monitors, design reconfiguration strategies, and obtain full-fledged FDIR components. We illustrate the approach on a case study inspired from autonomous robotics applications.

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“…Such restriction guaranteed the decidability on both the reachability problem and the language inclusion problem. Integer reset TAs [27,28] was a subclass of classical TAs since it can reset a clock only when it has integer value. Integer reset TAs were less expressive than classical TAs.…”

Section: Consists Of the Followingmentioning

confidence: 99%

Updatable timed automata with one updatable clock

Wen

Yuen

2017

Sci. China Inf. Sci.

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Updatable timed automata (UTAs) proposed by Bouyer et.al., is an extension of timed automata (TAs) having the extra ability to update clocks in a more elaborate way than simply reset them to zero. The reachability of UTAs is generally undecidable, which can be easily gained by regarding a pair of clocks as updatable counters. This paper investigates a subclass of UTAs by restricting the number of updatable clocks to be one. We will show that (1) the reachability of general UTAs with one updatable clock (UTA1s) is still undecidable, and (2) that of UTA1s under diagonal-free constraints is decidable, and the complexity is Pspace-complete. The former is achieved by encoding Minsky machines to the general UTA1s, where two counters are simulated by the updatable clock. The latter is gained by regarding a region of a UTA1 to be an unbounded digiword, and encoding sets of digiwords that are accepted by a one counter automaton where regions are generated as the value of the counter.

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Determinization and Expressiveness of Integer Reset Timed Automata with Silent Transitions

Cited by 3 publications

References 8 publications

Integer Reset Timed Automata: Clock Reduction and Determinizability

Integer Reset Timed Automata: Clock Reduction and Determinizability

Designing Systems with Detection and Reconfiguration Capabilities: A Formal Approach

Updatable timed automata with one updatable clock

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