Deterministic integration of single nanowire devices with on-chip photonics and electronics

Advanced transfer printing with in-situ optical monitoring for the integration of micron-scale devices

“…The second challenge for serial printing of ultra-compact devices within micrometre scale footprints is that the transfer stamp will come into contact with previously printed devices in subsequent transfer runs. The deterministic transfer of NW devices has been addressed by us in a recent review, where a number of complementary techniques are discussed [31]. Deterministic transfer printing of single NW devices has been demonstrated with absolute accuracy in the few hundred nanometres range [23], [31].…”

“…The deterministic transfer of NW devices has been addressed by us in a recent review, where a number of complementary techniques are discussed [31]. Deterministic transfer printing of single NW devices has been demonstrated with absolute accuracy in the few hundred nanometres range [23], [31]. In the case of serial transfer printing of multiple NWs in close proximity, a two-stage printing process can be employed to address the repeatable release of devices onto the receiver and the challenge of avoiding re-pick up of pre-printed devices.…”

“…The adhesion competition between the 8:1 stamp and the low roughness receiver favours the receiver in a slow stamp release process, allowing transfer of the NWs with high spatial accuracy. By using automated image processing tools to locate the position and orientation of the NW within the microscope field of view, and relative to the transfer stage position, these devices can be printed with absolute positional accuracy in the few hundred nanometres range [23], [31]. Fig.…”

Growth of type I superlattice III-V heterostructure in horizontal nanowires enclosed in a silicon oxide template

“…The most mature integration routes for III-V semiconductor material on Si substrate involve the transfer of the grown crystal from a lattice matched substrate onto Si. Already employed in industry, these integration routes bypass the issue of lattice mismatch between III and V and Si but become difficult to implement at 8 ′ ' wafer sizes [5][6][7]. Conversely, any monolithic route involving the direct growth of III-V semiconductor material on Si has to contend with lattice mismatch between the Si substrate and the epitaxially grown III-V layer as a source of defects [8].…”

In-Plane III–V Nanowires on Si(1 1 0) with Quantum Wells by Selective Epitaxy in Templates

“…In industry, integration of III–V semiconductors on Si is accomplished by the transfer of III–V material grown on lattice-matched substrates onto a supporting Si wafer. , This method allows manufacturers to avoid lattice mismatch as a source of defects entirely but implies increased production complexity and a limited integration density. − On the other hand, monolithic integration can offer high integration densities in very competitive time frames, provided the issue of lattice-mismatch-borne defects − is addressed.…”